From patchwork Sat Feb 22 16:48:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Omair Javaid X-Patchwork-Id: 25137 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pd0-f199.google.com (mail-pd0-f199.google.com [209.85.192.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 051D1203C6 for ; Sat, 22 Feb 2014 16:49:29 +0000 (UTC) Received: by mail-pd0-f199.google.com with SMTP id fp1sf11952485pdb.2 for ; Sat, 22 Feb 2014 08:49:29 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=Xoj8CXkehwDFTkLxwbVbFbwuRKuwKmj/dG7I6xbl27M=; b=WPL5yzGM1V5O9x1C7AkYhK3IcW1AO5zTdlEDueD9KnZgTX2wOFYz99onajHvdjTONm YuBLd65p7lEpHZbENg0JwNT9bK/K05LvABqA5ImAALFbT9LMAub8mKO7OaaZYyj98EdZ Yh7imot0w7Wc/u8x49tHqV7kEEZQs3P079tBWsqJo48Y6lbSCK4z1DzM9x2powSHW65M oTOXDmS+XgqYmwJNKYVzasAEcMUNrwPpiz51KrN9INj9E7O89mjel4/25edBvrT1tlkY tVpY5dHI7isOgh85KPwjljPtB7+BaU3mtK9nK/7rlCFvXP1l3ri6V5nnpdvBiUFUTmDy 7D6A== X-Gm-Message-State: ALoCoQliyDT3lCNncHwu5iR4n9vC7qeDTrltMUuDFT1uWHXJeNTcXVrqhrqQEOA0SVzWeZ8ESehE X-Received: by 10.66.189.228 with SMTP id gl4mr7150375pac.26.1393087769051; Sat, 22 Feb 2014 08:49:29 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.91.110 with SMTP id y101ls1488597qgd.0.gmail; Sat, 22 Feb 2014 08:49:28 -0800 (PST) X-Received: by 10.52.135.65 with SMTP id pq1mr6866512vdb.13.1393087768889; Sat, 22 Feb 2014 08:49:28 -0800 (PST) Received: from mail-ve0-f176.google.com (mail-ve0-f176.google.com [209.85.128.176]) by mx.google.com with ESMTPS id or7si4264042vcb.136.2014.02.22.08.49.28 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 22 Feb 2014 08:49:28 -0800 (PST) Received-SPF: neutral (google.com: 209.85.128.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.176; Received: by mail-ve0-f176.google.com with SMTP id jx11so4360729veb.35 for ; Sat, 22 Feb 2014 08:49:28 -0800 (PST) X-Received: by 10.52.246.227 with SMTP id xz3mr6876432vdc.95.1393087768801; Sat, 22 Feb 2014 08:49:28 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp114923vcz; Sat, 22 Feb 2014 08:49:28 -0800 (PST) X-Received: by 10.15.99.201 with SMTP id bl49mr15196069eeb.53.1393087767680; Sat, 22 Feb 2014 08:49:27 -0800 (PST) Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by mx.google.com with ESMTPS id a41si23514308eef.92.2014.02.22.08.49.27 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 22 Feb 2014 08:49:27 -0800 (PST) Received-SPF: neutral (google.com: 74.125.83.49 is neither permitted nor denied by best guess record for domain of omair.javaid@linaro.org) client-ip=74.125.83.49; Received: by mail-ee0-f49.google.com with SMTP id d17so2219297eek.8 for ; Sat, 22 Feb 2014 08:49:27 -0800 (PST) X-Received: by 10.15.75.193 with SMTP id l41mr15004702eey.114.1393087767147; Sat, 22 Feb 2014 08:49:27 -0800 (PST) Received: from localhost.localdomain ([175.110.189.84]) by mx.google.com with ESMTPSA id a2sm25596112eem.18.2014.02.22.08.49.24 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 22 Feb 2014 08:49:26 -0800 (PST) From: Omair Javaid To: gdb-patches@sourceware.org Cc: patches@linaro.org, Omair Javaid Subject: [PATCH 2/5] Support for recording thumb2 ASIMD struct load/store instructions Date: Sat, 22 Feb 2014 21:48:52 +0500 Message-Id: <1393087735-19261-3-git-send-email-omair.javaid@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1393087735-19261-1-git-send-email-omair.javaid@linaro.org> References: <1393087735-19261-1-git-send-email-omair.javaid@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: omair.javaid@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , gdb: 2013-02-22 Omair Javaid * arm-tdep.c (thumb2_record_asimd_struct_ld_st): New function. (thumb2_record_decode_insn_handler): Updated. --- gdb/arm-tdep.c | 194 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 193 insertions(+), 1 deletion(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 5eb7b12..76466c4 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -12975,6 +12975,198 @@ thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r) return arm_record_asimd_vfp_coproc (thumb2_insn_r); } +/* Record handler for advance SIMD structure load/store instructions. */ + +static int +thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r) +{ + struct regcache *reg_cache = thumb2_insn_r->regcache; + uint32_t l_bit, a_bit, b_bits; + uint32_t record_buf[128], record_buf_mem[128]; + uint32_t reg_rn, reg_vd, address, f_esize, f_elem; + uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0; + uint8_t bf_align, f_alignment, f_ebytes; + + l_bit = bit (thumb2_insn_r->arm_insn, 21); + a_bit = bit (thumb2_insn_r->arm_insn, 23); + b_bits = bits (thumb2_insn_r->arm_insn, 8, 11); + bf_align = bits (thumb2_insn_r->arm_insn, 4, 5); + reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); + reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15); + reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd; + f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7)); + f_esize = 8 * f_ebytes; + f_elem = 8 / f_ebytes; + + if (!l_bit) + { + ULONGEST u_regval = 0; + regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); + address = u_regval; + + if (!a_bit) + { + /* Handle VST1. */ + if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) + { + if (b_bits == 0x07) + bf_regs = 1; + else if (b_bits == 0x0a) + bf_regs = 2; + else if (b_bits == 0x06) + bf_regs = 3; + else if (b_bits == 0x02) + bf_regs = 4; + else + bf_regs = 0; + + for (index_r = 0; index_r < bf_regs; index_r++) + { + for (index_e = 0; index_e < f_elem; index_e++) + { + record_buf_mem[index_m++] = f_ebytes; + record_buf_mem[index_m++] = address; + address = address + f_ebytes; + thumb2_insn_r->mem_rec_count += 1; + } + } + } + /* Handle VST2. */ + else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) + { + if (b_bits == 0x09 || b_bits == 0x08) + bf_regs = 1; + else if (b_bits == 0x03) + bf_regs = 2; + else + bf_regs = 0; + + for (index_r = 0; index_r < bf_regs; index_r++) + for (index_e = 0; index_e < f_elem; index_e++) + { + for (loop_t = 0; loop_t < 2; loop_t++) + { + record_buf_mem[index_m++] = f_ebytes; + record_buf_mem[index_m++] = address + (loop_t * f_ebytes); + thumb2_insn_r->mem_rec_count += 1; + } + address = address + (2 * f_ebytes); + } + } + /* Handle VST3. */ + else if ((b_bits & 0x0e) == 0x04) + { + for (index_e = 0; index_e < f_elem; index_e++) + { + for (loop_t = 0; loop_t < 3; loop_t++) + { + record_buf_mem[index_m++] = f_ebytes; + record_buf_mem[index_m++] = address + (loop_t * f_ebytes); + thumb2_insn_r->mem_rec_count += 1; + } + address = address + (3 * f_ebytes); + } + } + /* Handle VST4. */ + else if (!(b_bits & 0x0e)) + { + for (index_e = 0; index_e < f_elem; index_e++) + { + for (loop_t = 0; loop_t < 4; loop_t++) + { + record_buf_mem[index_m++] = f_ebytes; + record_buf_mem[index_m++] = address + (loop_t * f_ebytes); + thumb2_insn_r->mem_rec_count += 1; + } + address = address + (4 * f_ebytes); + } + } + } + else + { + uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11); + + if (bft_size == 0x00) + f_ebytes = 1; + else if (bft_size == 0x01) + f_ebytes = 2; + else if (bft_size == 0x02) + f_ebytes = 4; + else + f_ebytes = 0; + + /* Handle VST1. */ + if (!(b_bits & 0x0b) || b_bits == 0x08) + thumb2_insn_r->mem_rec_count = 1; + /* Handle VST2. */ + else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09) + thumb2_insn_r->mem_rec_count = 2; + /* Handle VST3. */ + else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a) + thumb2_insn_r->mem_rec_count = 3; + /* Handle VST4. */ + else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b) + thumb2_insn_r->mem_rec_count = 4; + + for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++) + { + record_buf_mem[index_m] = f_ebytes; + record_buf_mem[index_m] = address + (index_m * f_ebytes); + } + } + } + else + { + if (!a_bit) + { + /* Handle VLD1. */ + if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) + thumb2_insn_r->reg_rec_count = 1; + /* Handle VLD2. */ + else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) + thumb2_insn_r->reg_rec_count = 2; + /* Handle VLD3. */ + else if ((b_bits & 0x0e) == 0x04) + thumb2_insn_r->reg_rec_count = 3; + /* Handle VLD4. */ + else if (!(b_bits & 0x0e)) + thumb2_insn_r->reg_rec_count = 4; + } + else + { + /* Handle VLD1. */ + if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c) + thumb2_insn_r->reg_rec_count = 1; + /* Handle VLD2. */ + else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d) + thumb2_insn_r->reg_rec_count = 2; + /* Handle VLD3. */ + else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e) + thumb2_insn_r->reg_rec_count = 3; + /* Handle VLD4. */ + else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f) + thumb2_insn_r->reg_rec_count = 4; + + for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++) + { + record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r; + } + } + } + + if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15) + { + record_buf[index_r] = reg_rn; + thumb2_insn_r->reg_rec_count += 1; + } + + REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, + record_buf); + MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, + record_buf_mem); + return 0; +} + /* Decodes thumb2 instruction type and invokes its record handler. */ static unsigned int @@ -13037,7 +13229,7 @@ thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) else if (!((op2 & 0x71) ^ 0x10)) { /* Advanced SIMD or structure load/store instructions. */ - return arm_record_unsupported_insn (thumb2_insn_r); + return thumb2_record_asimd_struct_ld_st (thumb2_insn_r); } else if (!((op2 & 0x67) ^ 0x01)) {