From patchwork Wed Aug 13 13:12:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Omair Javaid X-Patchwork-Id: 35355 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ob0-f198.google.com (mail-ob0-f198.google.com [209.85.214.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id E3F86203C5 for ; Wed, 13 Aug 2014 13:13:36 +0000 (UTC) Received: by mail-ob0-f198.google.com with SMTP id wp18sf52106845obc.1 for ; Wed, 13 Aug 2014 06:13:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=j+3CnwOTuw9ROPZ+Q9H9Bd8t5ibVX0hFemRGgvdv6XA=; b=VC1SzXLel+w+hT3CTpWq4TN/F7Y74Ngro1Gp8RwJ8gr/NdgKT3FMXBMC/UB1I0hSw9 g/Sfz4JUqMqbl7RJzjISBIT2luQ4zsxj61FEanOxdXKEUHHPziN80wAV/rIK+gGbEdeJ foOJhdl+q4TBRfsWQskD2iE+dxNNWK/ZsFPr+7dI32xJCHtpv2+A0VqbG0i0VcMcEaM8 esN1dZxgYJE8x3hmwpcmbVCVgRSpbCvj5tyX0HIirtpo0/pDEIpNquN9jVX+DZ8md6AR mExa6z4aNI9/uPQtKZ3q3wMv1YDF/TGhcYx8ko0UkrmG5B5SWOZzEtHKaS3ZftF1bYKQ J+gw== X-Gm-Message-State: ALoCoQmna4a7OtxFgBVGa13dTtQnvFar1X4zLQ8jAySb4dLgMXDzVsjA56AmslC4ZPjScPPVe6xO X-Received: by 10.182.125.68 with SMTP id mo4mr215530obb.49.1407935616556; Wed, 13 Aug 2014 06:13:36 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.50.107 with SMTP id r98ls578777qga.71.gmail; Wed, 13 Aug 2014 06:13:36 -0700 (PDT) X-Received: by 10.220.114.5 with SMTP id c5mr3538431vcq.28.1407935616467; Wed, 13 Aug 2014 06:13:36 -0700 (PDT) Received: from mail-vc0-f179.google.com (mail-vc0-f179.google.com [209.85.220.179]) by mx.google.com with ESMTPS id 7si1068306vcs.68.2014.08.13.06.13.36 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Aug 2014 06:13:36 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.179 as permitted sender) client-ip=209.85.220.179; Received: by mail-vc0-f179.google.com with SMTP id hq11so14994393vcb.38 for ; Wed, 13 Aug 2014 06:13:36 -0700 (PDT) X-Received: by 10.52.129.165 with SMTP id nx5mr2892879vdb.25.1407935616388; Wed, 13 Aug 2014 06:13:36 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp329768vcb; Wed, 13 Aug 2014 06:13:35 -0700 (PDT) X-Received: by 10.180.83.8 with SMTP id m8mr38916096wiy.8.1407935615282; Wed, 13 Aug 2014 06:13:35 -0700 (PDT) Received: from mail-we0-f176.google.com (mail-we0-f176.google.com [74.125.82.176]) by mx.google.com with ESMTPS id p5si2494588wiz.81.2014.08.13.06.13.34 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Aug 2014 06:13:35 -0700 (PDT) Received-SPF: pass (google.com: domain of omair.javaid@linaro.org designates 74.125.82.176 as permitted sender) client-ip=74.125.82.176; Received: by mail-we0-f176.google.com with SMTP id q58so11270356wes.7 for ; Wed, 13 Aug 2014 06:13:34 -0700 (PDT) X-Received: by 10.180.101.162 with SMTP id fh2mr4862429wib.11.1407935614503; Wed, 13 Aug 2014 06:13:34 -0700 (PDT) Received: from localhost.localdomain ([182.185.185.192]) by mx.google.com with ESMTPSA id w14sm50806711wij.2.2014.08.13.06.13.32 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 Aug 2014 06:13:33 -0700 (PDT) From: Omair Javaid To: gdb-patches@sourceware.org Cc: patches@linaro.org Subject: [PATCH v3 3/6] Implement support for recording VFP data processing instructions Date: Wed, 13 Aug 2014 18:12:12 +0500 Message-Id: <1407935535-27978-4-git-send-email-omair.javaid@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1407935535-27978-1-git-send-email-omair.javaid@linaro.org> References: <1407935535-27978-1-git-send-email-omair.javaid@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: omair.javaid@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , gdb: 2014-08-13 Omair Javaid * arm-tdep.c (arm_record_coproc_data_proc): Updated. (arm_record_vfp_data_proc_insn): Added record handler for VFP data processing instructions. --- gdb/arm-tdep.c | 213 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 212 insertions(+), 1 deletion(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index adee197..d003619 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -11990,6 +11990,217 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r) return -1; } +/* Record handler for arm/thumb mode VFP data processing instructions. */ + +static int +arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r) +{ + uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; + uint32_t record_buf[4]; + enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV}; + enum insn_types curr_insn_type = INSN_INV; + + reg_vd = bits (arm_insn_r->arm_insn, 12, 15); + opc1 = bits (arm_insn_r->arm_insn, 20, 23); + opc2 = bits (arm_insn_r->arm_insn, 16, 19); + opc3 = bits (arm_insn_r->arm_insn, 6, 7); + dp_op_sz = bit (arm_insn_r->arm_insn, 8); + bit_d = bit (arm_insn_r->arm_insn, 22); + opc1 = opc1 & 0x04; + + /* Handle VMLA, VMLS. */ + if (opc1 == 0x00) + { + if (bit (arm_insn_r->arm_insn, 10)) + { + if (bit (arm_insn_r->arm_insn, 6)) + curr_insn_type = INSN_T0; + else + curr_insn_type = INSN_T1; + } + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VNMLA, VNMLS, VNMUL. */ + else if (opc1 == 0x01) + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + /* Handle VMUL. */ + else if (opc1 == 0x02 && !(opc3 & 0x01)) + { + if (bit (arm_insn_r->arm_insn, 10)) + { + if (bit (arm_insn_r->arm_insn, 6)) + curr_insn_type = INSN_T0; + else + curr_insn_type = INSN_T1; + } + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VADD, VSUB. */ + else if (opc1 == 0x03) + { + if (!bit (arm_insn_r->arm_insn, 9)) + { + if (bit (arm_insn_r->arm_insn, 6)) + curr_insn_type = INSN_T0; + else + curr_insn_type = INSN_T1; + } + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VDIV. */ + else if (opc1 == 0x0b) + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + /* Handle all other vfp data processing instructions. */ + else if (opc1 == 0x0b) + { + /* Handle VMOV. */ + if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01)) + { + if (bit (arm_insn_r->arm_insn, 4)) + { + if (bit (arm_insn_r->arm_insn, 6)) + curr_insn_type = INSN_T0; + else + curr_insn_type = INSN_T1; + } + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VNEG and VABS. */ + else if ((opc2 == 0x01 && opc3 == 0x01) + || (opc2 == 0x00 && opc3 == 0x03)) + { + if (!bit (arm_insn_r->arm_insn, 11)) + { + if (bit (arm_insn_r->arm_insn, 6)) + curr_insn_type = INSN_T0; + else + curr_insn_type = INSN_T1; + } + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VSQRT. */ + else if (opc2 == 0x01 && opc3 == 0x03) + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + /* Handle VCVT. */ + else if (opc2 == 0x07 && opc3 == 0x03) + { + if (!dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + else if (opc3 & 0x01) + { + /* Handle VCVT. */ + if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c) + { + if (!bit (arm_insn_r->arm_insn, 18)) + curr_insn_type = INSN_T2; + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VCVT. */ + else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e) + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + /* Handle VCVTB, VCVTT. */ + else if ((opc2 & 0x0e) == 0x02) + curr_insn_type = INSN_T2; + /* Handle VCMP, VCMPE. */ + else if ((opc2 & 0x0e) == 0x04) + curr_insn_type = INSN_T3; + } + } + + switch (curr_insn_type) + { + case INSN_T0: + reg_vd = reg_vd | (bit_d << 4); + record_buf[0] = reg_vd + ARM_D0_REGNUM; + record_buf[1] = reg_vd + ARM_D0_REGNUM + 1; + arm_insn_r->reg_rec_count = 2; + break; + + case INSN_T1: + reg_vd = reg_vd | (bit_d << 4); + record_buf[0] = reg_vd + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + break; + + case INSN_T2: + reg_vd = (reg_vd << 1) | bit_d; + record_buf[0] = reg_vd + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + break; + + case INSN_T3: + record_buf[0] = ARM_FPSCR_REGNUM; + arm_insn_r->reg_rec_count = 1; + break; + + default: + gdb_assert_not_reached ("no decoding pattern found"); + break; + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + return 0; +} + /* Handling opcode 110 insns. */ static int @@ -12089,7 +12300,7 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) { /* VFP data-processing instructions. */ if (!op1_sbit && !op) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_vfp_data_proc_insn (arm_insn_r); /* Advanced SIMD, VFP instructions. */ if (!op1_sbit && op)