From patchwork Sat Jan 14 19:21:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 91513 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp747877qgi; Sat, 14 Jan 2017 11:21:35 -0800 (PST) X-Received: by 10.84.216.86 with SMTP id f22mr38671866plj.117.1484421694994; Sat, 14 Jan 2017 11:21:34 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id j3si8275036pld.116.2017.01.14.11.21.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 14 Jan 2017 11:21:34 -0800 (PST) Received-SPF: pass (google.com: domain of gdb-patches-return-136220-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of gdb-patches-return-136220-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gdb-patches-return-136220-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :cc:content-type; q=dns; s=default; b=NN3btZIA/8e4JM/j8Zu7ypaJjh aO232yY7mG42/nDi9Ntbuh0QNxiCpLX129HwO5LxtqRAtGy5ZAe8e+PkdEXU/7YE 4YVCM/Szp5VLX77qTaISqRL+BuT1zrtHA/ikp/QsZWxTS5mETT8EBVn+PMCV8vGw E1Lzy0aLZr/UVMDDE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :cc:content-type; s=default; bh=w2lvvJ+G17Q1Id5AJUt38jh1Lu0=; b= msKhZDNZn14Q/iYu468w5gkstHoO9gPV+VnE829DhISl0PGYes7TiuW7sEj8xevB IzjdU3qk5h7wRdPbwhV2mzmOS0/OXCVY7+wZZ0PnVdC+QHqD8vO9DuxC5x+QIpC+ HORgZ08HsDDsJHOyWiS7Zz6k20akysGm6cQ0XDRXKSI= Received: (qmail 99404 invoked by alias); 14 Jan 2017 19:21:27 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 99389 invoked by uid 89); 14 Jan 2017 19:21:25 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.4 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=no version=3.3.2 spammy=Hx-languages-length:3342 X-HELO: mail-yw0-f182.google.com Received: from mail-yw0-f182.google.com (HELO mail-yw0-f182.google.com) (209.85.161.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 14 Jan 2017 19:21:15 +0000 Received: by mail-yw0-f182.google.com with SMTP id l19so49003901ywc.2 for ; Sat, 14 Jan 2017 11:21:14 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=EHFE3DOnMn6ZLRqNwGvSy0b0hHBP0GejxwqvBxypOWw=; b=sFPtNk3Evv40wjdnsYI7iS0J5Xdxz9m0wJRVyEUBHLQfTDVlJJsrHYo1R/faa9IUEO pTxWOp6heCeHRgWkBFewbPPDsGROKWNpuMY+ypyQZkRQhpTqaCa+C2PsyW6XSr2jN/xD uH6tvZssd4JGyvyQW681S9THVozu0jB31QWc9+R06iqvPNHSEzdPwn8FZmb0gqJCEI0g e/WAoVnRhHzb4PKF33B1/7+FIxInskhWdvRGrLPzDzA5T74smrG9oTBaEnA7SxCjasu6 rc07hM/28wuqLmPKjQlqkSRaWExAOEIIN13bVsMBD1r1vxLfWRKW4VoV9fnQ51M7nfw/ 4Khw== X-Gm-Message-State: AIkVDXJki+W3Y1CE6CiiN+0ebJ87lLsGsrwDrk6RPjSXtI/9SYMeljj7M2rZsUabVwHcRrzEWzrJsOGPvufoh5QV X-Received: by 10.129.4.71 with SMTP id 68mr18112935ywe.333.1484421673528; Sat, 14 Jan 2017 11:21:13 -0800 (PST) MIME-Version: 1.0 Received: by 10.129.92.4 with HTTP; Sat, 14 Jan 2017 11:21:13 -0800 (PST) From: Jim Wilson Date: Sat, 14 Jan 2017 11:21:13 -0800 Message-ID: Subject: [PATCH] aarch64 sim xtn2 bug fix To: gdb-patches@sourceware.org Cc: Nick Clifton The code is applying a bias (shift) to inputs which is wrong. The index in case 2 should be i + 2 not i + 4. We can simplify the code a little and remove the if statement, reducing 7 lines to 3 in each of the 3 cases. The testcase works with the patch, and fails without. The patch reduces GCC C testsuite failures from 2174 to 2108 (-66). Jim sim/aarch64/ * simulator.c (do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to i + 2. Delete if on bias, change index to i + bias * X. sim/testsuite/sim/aarch64/ * xtn.s: New. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 36129e5..c8e65c5 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -4206,33 +4203,21 @@ do_vec_XTN (sim_cpu *cpu) switch (INSTR (23, 22)) { case 0: - if (bias) - for (i = 0; i < 8; i++) - aarch64_set_vec_u8 (cpu, vd, i + 8, - aarch64_get_vec_u16 (cpu, vs, i) >> 8); - else - for (i = 0; i < 8; i++) - aarch64_set_vec_u8 (cpu, vd, i, aarch64_get_vec_u16 (cpu, vs, i)); + for (i = 0; i < 8; i++) + aarch64_set_vec_u8 (cpu, vd, i + (bias * 8), + aarch64_get_vec_u16 (cpu, vs, i)); return; case 1: - if (bias) - for (i = 0; i < 4; i++) - aarch64_set_vec_u16 (cpu, vd, i + 4, - aarch64_get_vec_u32 (cpu, vs, i) >> 16); - else - for (i = 0; i < 4; i++) - aarch64_set_vec_u16 (cpu, vd, i, aarch64_get_vec_u32 (cpu, vs, i)); + for (i = 0; i < 4; i++) + aarch64_set_vec_u16 (cpu, vd, i + (bias * 4), + aarch64_get_vec_u32 (cpu, vs, i)); return; case 2: - if (bias) - for (i = 0; i < 2; i++) - aarch64_set_vec_u32 (cpu, vd, i + 4, - aarch64_get_vec_u64 (cpu, vs, i) >> 32); - else - for (i = 0; i < 2; i++) - aarch64_set_vec_u32 (cpu, vd, i, aarch64_get_vec_u64 (cpu, vs, i)); + for (i = 0; i < 2; i++) + aarch64_set_vec_u32 (cpu, vd, i + (bias * 2), + aarch64_get_vec_u64 (cpu, vs, i)); return; } } diff --git a/sim/testsuite/sim/aarch64/xtn.s b/sim/testsuite/sim/aarch64/xtn.s new file mode 100644 index 0000000..de369f7 --- /dev/null +++ b/sim/testsuite/sim/aarch64/xtn.s @@ -0,0 +1,79 @@ +# mach: aarch64 + +# Check the extract narrow instructions: xtn, xtn2. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +input2: + .word 0x14131211 + .word 0x18171615 + .word 0x1c1b1a19 + .word 0x201f1e1d +x16b: + .word 0x07050301 + .word 0x0f0d0b09 + .word 0x17151311 + .word 0x1f1d1b19 +x8h: + .word 0x06050201 + .word 0x0e0d0a09 + .word 0x16151211 + .word 0x1e1d1a19 +x4s: + .word 0x04030201 + .word 0x0c0b0a09 + .word 0x14131211 + .word 0x1c1b1a19 + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + adrp x0, input2 + ldr q1, [x0, #:lo12:input2] + + xtn v2.8b, v0.8h + xtn2 v2.16b, v1.8h + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, x16b + ldr x4, [x3, #:lo12:x16b] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:x16b+8] + cmp x2, x5 + bne .Lfailure + + xtn v2.4h, v0.4s + xtn2 v2.8h, v1.4s + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, x8h + ldr x4, [x3, #:lo12:x8h] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:x8h+8] + cmp x2, x5 + bne .Lfailure + + xtn v2.2s, v0.2d + xtn2 v2.4s, v1.2d + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, x4s + ldr x4, [x3, #:lo12:x4s] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:x4s+8] + cmp x2, x5 + bne .Lfailure + + pass +.Lfailure: + fail