From patchwork Sat Apr 8 14:27:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 97050 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp702121qgd; Sat, 8 Apr 2017 07:27:32 -0700 (PDT) X-Received: by 10.99.112.18 with SMTP id l18mr47342013pgc.142.1491661652809; Sat, 08 Apr 2017 07:27:32 -0700 (PDT) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id u129si8264607pgc.340.2017.04.08.07.27.32 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 Apr 2017 07:27:32 -0700 (PDT) Received-SPF: pass (google.com: domain of gdb-patches-return-138108-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of gdb-patches-return-138108-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gdb-patches-return-138108-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :content-type; q=dns; s=default; b=O/MuqbH8U98QCXizA2p4j9gbc58ny N1u7v+cPrKfDxK5ztWGarZEhZpxPrfLj49oug78HFklZzyef1kNDUu3cwKgiz3da mhes+gOEQuRz8dA5KtI7fOL1T3UDZi5c+zuOJ1gIYyn7jiBspQqNEPbZoTsPbHvs T+a8DIUOD4uoFo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :content-type; s=default; bh=AEQ0km5TY52OopvMow5H3Qh3gak=; b=cDl M0bdQz2hVpypR45PM0faN47ubFap3b+kQOaKaY0Ckwwn9QRYUggQIzBrjQQ+bR7R Pffzm4hCUsoH4VWxXqbLmuMsX86JI/NVJrvr5rv6NEaBbbf+SLX/uX6NfG+yzKmw 4jAuXhjSughUfg35Yg1xVSwj/Fc4cbDNw0OEabd4= Received: (qmail 66244 invoked by alias); 8 Apr 2017 14:27:20 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 66201 invoked by uid 89); 8 Apr 2017 14:27:19 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-lf0-f41.google.com Received: from mail-lf0-f41.google.com (HELO mail-lf0-f41.google.com) (209.85.215.41) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 08 Apr 2017 14:27:17 +0000 Received: by mail-lf0-f41.google.com with SMTP id s141so17996929lfe.3 for ; Sat, 08 Apr 2017 07:27:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=pUg6BDZ8498c2tuAxdgB2CNMO88kr+/9Ccru5Af7r2M=; b=c8SSqzPxK1FzzC7eaQUCXTudIynkvO1M7ZLvfAr6nZBhx46g1CDEdKBxE91yJ1pefp P7BejUZheAKYimF6kP3qgV/1uvhx19rBCz+ke/ddD1F8hehkI8R1diKo7enrGXQUQuEg LjHZKlcn/SBZ9bHR1KrKgFfiAhJQQlrfWOON6Suyr7ZBL0X8ULykqmG4szyJTzDyOhkp UWNWGa51y7CJ/gi+g6kBpOS3XtdILunuYQAWvKJJ3wkaL9d+lI9M1vIM3oIZUM7KjAZh NiaZdzlkafpmqYNvOnlFY0GaygMxClo6d4n+gbc7PO8RKDxlZ1/+9fOjbltzkzp/y4CX TVdg== X-Gm-Message-State: AFeK/H27UoAEx8Ew5Ub7cz56OBLj/+jRfjkbcAckvhIg0qC20Ssn5l0l7iViiXda2+B2jhotqxYsly9j9j9Kb1nj X-Received: by 10.25.89.135 with SMTP id n129mr12836321lfb.180.1491661636485; Sat, 08 Apr 2017 07:27:16 -0700 (PDT) MIME-Version: 1.0 Received: by 10.25.162.145 with HTTP; Sat, 8 Apr 2017 07:27:15 -0700 (PDT) From: Jim Wilson Date: Sat, 8 Apr 2017 07:27:15 -0700 Message-ID: Subject: [PATCH] aarch64 sim fcmXX zero instructions To: gdb-patches@sourceware.org This patch adds support for the fcmXX zero instructions. The new testcase fails without the patch, and works with the patch. The GCC C testsuite failures drop from 1438 to 1431 (-7). Jim 2017-04-08 Jim Wilson sim/aarch64/ * simulator.c (do_scalar_FCMGE_zero): New. (do_scalar_FCMLE_zero, do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero) (do_scalar_FCMLT_zero): Likewise. (do_scalar_vec): Add calls to new functions. sim/testsuite/sim/aarch64/ * fcmXX.s: New. (diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index f0668ad..c2e02b1 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -8926,6 +8926,146 @@ do_scalar_SSHL (sim_cpu *cpu) aarch64_get_vec_s64 (cpu, rn, 0) >> - shift); } +/* Floating point scalar compare greater than or equal to 0. */ +static void +do_scalar_FCMGE_zero (sim_cpu *cpu) +{ + /* instr [31,23] = 0111 1110 1 + instr [22,22] = size + instr [21,16] = 1000 00 + instr [15,10] = 1100 10 + instr [9, 5] = Rn + instr [4, 0] = Rd. */ + + unsigned size = INSTR (22, 22); + unsigned rn = INSTR (9, 5); + unsigned rd = INSTR (4, 0); + + NYI_assert (31, 23, 0x0FD); + NYI_assert (21, 16, 0x20); + NYI_assert (15, 10, 0x32); + + TRACE_DECODE (cpu, "emulated at line %d", __LINE__); + if (size) + aarch64_set_vec_u64 (cpu, rd, 0, + aarch64_get_vec_double (cpu, rn, 0) >= 0.0 ? -1 : 0); + else + aarch64_set_vec_u32 (cpu, rd, 0, + aarch64_get_vec_float (cpu, rn, 0) >= 0.0 ? -1 : 0); +} + +/* Floating point scalar compare less than or equal to 0. */ +static void +do_scalar_FCMLE_zero (sim_cpu *cpu) +{ + /* instr [31,23] = 0111 1110 1 + instr [22,22] = size + instr [21,16] = 1000 00 + instr [15,10] = 1101 10 + instr [9, 5] = Rn + instr [4, 0] = Rd. */ + + unsigned size = INSTR (22, 22); + unsigned rn = INSTR (9, 5); + unsigned rd = INSTR (4, 0); + + NYI_assert (31, 23, 0x0FD); + NYI_assert (21, 16, 0x20); + NYI_assert (15, 10, 0x36); + + TRACE_DECODE (cpu, "emulated at line %d", __LINE__); + if (size) + aarch64_set_vec_u64 (cpu, rd, 0, + aarch64_get_vec_double (cpu, rn, 0) <= 0.0 ? -1 : 0); + else + aarch64_set_vec_u32 (cpu, rd, 0, + aarch64_get_vec_float (cpu, rn, 0) <= 0.0 ? -1 : 0); +} + +/* Floating point scalar compare greater than 0. */ +static void +do_scalar_FCMGT_zero (sim_cpu *cpu) +{ + /* instr [31,23] = 0101 1110 1 + instr [22,22] = size + instr [21,16] = 1000 00 + instr [15,10] = 1100 10 + instr [9, 5] = Rn + instr [4, 0] = Rd. */ + + unsigned size = INSTR (22, 22); + unsigned rn = INSTR (9, 5); + unsigned rd = INSTR (4, 0); + + NYI_assert (31, 23, 0x0BD); + NYI_assert (21, 16, 0x20); + NYI_assert (15, 10, 0x32); + + TRACE_DECODE (cpu, "emulated at line %d", __LINE__); + if (size) + aarch64_set_vec_u64 (cpu, rd, 0, + aarch64_get_vec_double (cpu, rn, 0) > 0.0 ? -1 : 0); + else + aarch64_set_vec_u32 (cpu, rd, 0, + aarch64_get_vec_float (cpu, rn, 0) > 0.0 ? -1 : 0); +} + +/* Floating point scalar compare equal to 0. */ +static void +do_scalar_FCMEQ_zero (sim_cpu *cpu) +{ + /* instr [31,23] = 0101 1110 1 + instr [22,22] = size + instr [21,16] = 1000 00 + instr [15,10] = 1101 10 + instr [9, 5] = Rn + instr [4, 0] = Rd. */ + + unsigned size = INSTR (22, 22); + unsigned rn = INSTR (9, 5); + unsigned rd = INSTR (4, 0); + + NYI_assert (31, 23, 0x0BD); + NYI_assert (21, 16, 0x20); + NYI_assert (15, 10, 0x36); + + TRACE_DECODE (cpu, "emulated at line %d", __LINE__); + if (size) + aarch64_set_vec_u64 (cpu, rd, 0, + aarch64_get_vec_double (cpu, rn, 0) == 0.0 ? -1 : 0); + else + aarch64_set_vec_u32 (cpu, rd, 0, + aarch64_get_vec_float (cpu, rn, 0) == 0.0 ? -1 : 0); +} + +/* Floating point scalar compare less than 0. */ +static void +do_scalar_FCMLT_zero (sim_cpu *cpu) +{ + /* instr [31,23] = 0101 1110 1 + instr [22,22] = size + instr [21,16] = 1000 00 + instr [15,10] = 1110 10 + instr [9, 5] = Rn + instr [4, 0] = Rd. */ + + unsigned size = INSTR (22, 22); + unsigned rn = INSTR (9, 5); + unsigned rd = INSTR (4, 0); + + NYI_assert (31, 23, 0x0BD); + NYI_assert (21, 16, 0x20); + NYI_assert (15, 10, 0x3A); + + TRACE_DECODE (cpu, "emulated at line %d", __LINE__); + if (size) + aarch64_set_vec_u64 (cpu, rd, 0, + aarch64_get_vec_double (cpu, rn, 0) < 0.0 ? -1 : 0); + else + aarch64_set_vec_u32 (cpu, rd, 0, + aarch64_get_vec_float (cpu, rn, 0) < 0.0 ? -1 : 0); +} + static void do_scalar_shift (sim_cpu *cpu) { @@ -9249,7 +9389,9 @@ do_scalar_vec (sim_cpu *cpu) case 0x0D: do_scalar_CMGT (cpu); return; case 0x11: do_scalar_USHL (cpu); return; case 0x2E: do_scalar_NEG (cpu); return; + case 0x32: do_scalar_FCMGE_zero (cpu); return; case 0x35: do_scalar_FABD (cpu); return; + case 0x36: do_scalar_FCMLE_zero (cpu); return; case 0x39: do_scalar_FCM (cpu); return; case 0x3B: do_scalar_FCM (cpu); return; default: @@ -9263,6 +9405,9 @@ do_scalar_vec (sim_cpu *cpu) { case 0x21: do_double_add (cpu); return; case 0x11: do_scalar_SSHL (cpu); return; + case 0x32: do_scalar_FCMGT_zero (cpu); return; + case 0x36: do_scalar_FCMEQ_zero (cpu); return; + case 0x3A: do_scalar_FCMLT_zero (cpu); return; default: HALT_NYI; } diff --git a/sim/testsuite/sim/aarch64/fcmXX.s b/sim/testsuite/sim/aarch64/fcmXX.s new file mode 100644 index 0000000..cc1a2a9 --- /dev/null +++ b/sim/testsuite/sim/aarch64/fcmXX.s @@ -0,0 +1,77 @@ +# mach: aarch64 + +# Check the FP scalar compare zero instructions: fcmeq, fcmle, fcmlt, fcmge, +# fcmgt. +# Check values -1, 0, and 1. + +.include "testutils.inc" + + start + fmov s0, wzr + fcmeq s1, s0, #0.0 + mov w0, v1.s[0] + cmp w0, #-1 + bne .Lfailure + fmov s0, #-1.0 + fcmeq s1, s0, #0.0 + mov w0, v1.s[0] + cmp w0, #0 + bne .Lfailure + fmov d0, xzr + fcmeq d1, d0, #0.0 + mov x0, v1.d[0] + cmp x0, #-1 + bne .Lfailure + fmov d0, #1.0 + fcmeq d1, d0, #0.0 + mov x0, v1.d[0] + cmp x0, #0 + bne .Lfailure + + fmov s0, #-1.0 + fcmle s1, s0, #0.0 + mov w0, v1.s[0] + cmp w0, #-1 + bne .Lfailure + fmov d0, #-1.0 + fcmle d1, d0, #0.0 + mov x0, v1.d[0] + cmp x0, #-1 + bne .Lfailure + + fmov s0, #-1.0 + fcmlt s1, s0, #0.0 + mov w0, v1.s[0] + cmp w0, #-1 + bne .Lfailure + fmov d0, #-1.0 + fcmlt d1, d0, #0.0 + mov x0, v1.d[0] + cmp x0, #-1 + bne .Lfailure + + fmov s0, #1.0 + fcmge s1, s0, #0.0 + mov w0, v1.s[0] + cmp w0, #-1 + bne .Lfailure + fmov d0, #1.0 + fcmge d1, d0, #0.0 + mov x0, v1.d[0] + cmp x0, #-1 + bne .Lfailure + + fmov s0, #1.0 + fcmgt s1, s0, #0.0 + mov w0, v1.s[0] + cmp w0, #-1 + bne .Lfailure + fmov d0, #1.0 + fcmgt d1, d0, #0.0 + mov x0, v1.d[0] + cmp x0, #-1 + bne .Lfailure + + pass +.Lfailure: + fail