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[2001:770:15f::2]) by mx.google.com with ESMTPS id em8si14790718wjd.147.2014.03.04.02.29.02 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Mar 2014 02:29:02 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:770:15f::2 as permitted sender) client-ip=2001:770:15f::2; Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WKmac-0003rF-61; Tue, 04 Mar 2014 10:28:46 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WKmaa-0006tX-5w; Tue, 04 Mar 2014 10:28:44 +0000 Received: from fw-tnat.austin.arm.com ([217.140.110.23] helo=collaborate-mta1.arm.com) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WKmaX-0006rB-Hf for linux-arm-kernel@lists.infradead.org; Tue, 04 Mar 2014 10:28:41 +0000 Received: from arm.com (e102109-lin.cambridge.arm.com [10.1.203.182]) by collaborate-mta1.arm.com (Postfix) with ESMTPS id 3ADD313FBF3; Tue, 4 Mar 2014 04:28:18 -0600 (CST) Date: Tue, 4 Mar 2014 10:28:06 +0000 From: Catalin Marinas To: Mark Brown Subject: Re: [PATCH v2] arm64: topology: Implement basic CPU topology support Message-ID: <20140304102806.GH30596@arm.com> References: <1393919477-27814-1-git-send-email-broonie@kernel.org> <20140304095534.GE30596@arm.com> <20140304101641.GK13126@sirena.org.uk> MIME-Version: 1.0 In-Reply-To: <20140304101641.GK13126@sirena.org.uk> User-Agent: Mutt/1.5.20 (2009-06-14) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140304_052841_629586_70B1EC57 X-CRM114-Status: GOOD ( 16.90 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Mark Rutland , Lorenzo Pieralisi , Will Deacon , "linaro-kernel@lists.linaro.org" , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: catalin.marinas@arm.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Content-Disposition: inline On Tue, Mar 04, 2014 at 10:16:41AM +0000, Mark Brown wrote: > On Tue, Mar 04, 2014 at 09:55:36AM +0000, Catalin Marinas wrote: > > On Tue, Mar 04, 2014 at 07:51:17AM +0000, Mark Brown wrote: > > > > +config CPU_TOPOLOGY > > > + bool "Support CPU topology definition" > > > Thanks for the patch. I applied it but not pushed to -next yet. I wonder > > whether it makes sense to drop the description of the CPU_TOPOLOGY entry > > here so that it is no longer selectable. It will be enabled by default > > when SMP (I can do the change myself, no need to repost). > > I'm totally fine with that, I only made it selectable due to the 32 bit > code doing that - I'm not sure we even need the separate symbol. > Whatever you prefer. Like that? diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 4474e247f94a..140cd1a9dc0c 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -165,17 +165,9 @@ config SMP If you don't know what to do here, say N. -config CPU_TOPOLOGY - bool "Support CPU topology definition" - depends on SMP - default y - help - Support CPU topology definition, based on configuration - provided by the firmware. - config SCHED_MC bool "Multi-core scheduler support" - depends on CPU_TOPOLOGY + depends on SMP help Multi-core scheduler support improves the CPU scheduler's decision making when dealing with multi-core CPU chips at a cost of slightly @@ -183,7 +175,7 @@ config SCHED_MC config SCHED_SMT bool "SMT scheduler support" - depends on CPU_TOPOLOGY + depends on SMP help Improves the CPU scheduler's decision making when dealing with MultiThreading at a cost of slightly increased overhead in some diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h index c8a47e8f452b..0172e6d76bf3 100644 --- a/arch/arm64/include/asm/topology.h +++ b/arch/arm64/include/asm/topology.h @@ -1,7 +1,7 @@ #ifndef __ASM_TOPOLOGY_H #define __ASM_TOPOLOGY_H -#ifdef CONFIG_CPU_TOPOLOGY +#ifdef CONFIG_SMP #include diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index da1dafb3db87..cfee8273fccb 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -14,14 +14,13 @@ arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \ arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \ sys_compat.o arm64-obj-$(CONFIG_MODULES) += arm64ksyms.o module.o -arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o +arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o topology.o arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND) += sleep.o suspend.o arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o arm64-obj-$(CONFIG_KGDB) += kgdb.o -arm64-obj-$(CONFIG_CPU_TOPOLOGY) += topology.o obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m)