From patchwork Fri Aug 24 08:29:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 10918 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 46FE923E41 for ; Fri, 24 Aug 2012 08:30:34 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 3D35DA187DB for ; Fri, 24 Aug 2012 08:30:17 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id j25so671343iaf.11 for ; Fri, 24 Aug 2012 01:30:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf :x-pgp-universal:from:to:date:message-id:x-mailer:in-reply-to :references:mime-version:cc:subject:x-beenthere:x-mailman-version :precedence:list-id:list-unsubscribe:list-archive:list-post :list-help:list-subscribe:content-type:content-transfer-encoding :sender:errors-to:x-gm-message-state; bh=1b8B3v2Vjmy4YpGnedBIvkGylbuU+eaCniuATPt9Kaw=; b=aFNGg0Rxko80bw6KpSe2ZVBzBuOd3nBaSPe5jou4e3EdHNEGVQM4NI9JJJnFGpp94e F9Kxw49iFeFrtxyYKuB/RIPJqwjzIkboXNcSX25UtWQEvI5WQPPyQzMY8kAoFYyJrLUo wpszLoZdsvGK5niohVyNIuS6mgZTSqO6ZGmx8RcoPXZSsghsgTYRMXOlsHIDcx1Ig/CT RqoPbTLv1CtQgul100ElB3yoryTBnTCTam+7fnQSRoltMeRmqTVpwpm6qheHv74ChGN2 6dZ477+eYt2eA7amwBBXlmed7+XGEx0f6PNX03hhGwzPNliQUYacZroHRokWz6ASVZVk FN4g== Received: by 10.42.84.69 with SMTP id k5mr3759439icl.5.1345797033835; Fri, 24 Aug 2012 01:30:33 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp307524igc; Fri, 24 Aug 2012 01:30:33 -0700 (PDT) Received: by 10.180.107.2 with SMTP id gy2mr3728720wib.2.1345797032509; Fri, 24 Aug 2012 01:30:32 -0700 (PDT) Received: from mombin.canonical.com (mombin.canonical.com. [91.189.95.16]) by mx.google.com with ESMTP id z1si4114572wix.42.2012.08.24.01.30.31; Fri, 24 Aug 2012 01:30:32 -0700 (PDT) Received-SPF: neutral (google.com: 91.189.95.16 is neither permitted nor denied by best guess record for domain of linaro-mm-sig-bounces@lists.linaro.org) client-ip=91.189.95.16; Authentication-Results: mx.google.com; spf=neutral (google.com: 91.189.95.16 is neither permitted nor denied by best guess record for domain of linaro-mm-sig-bounces@lists.linaro.org) smtp.mail=linaro-mm-sig-bounces@lists.linaro.org Received: from localhost ([127.0.0.1] helo=mombin.canonical.com) by mombin.canonical.com with esmtp (Exim 4.71) (envelope-from ) id 1T4pHi-00042f-B6; Fri, 24 Aug 2012 08:30:30 +0000 Received: from hqemgate03.nvidia.com ([216.228.121.140]) by mombin.canonical.com with esmtp (Exim 4.71) (envelope-from ) id 1T4pHg-00042T-PW for linaro-mm-sig@lists.linaro.org; Fri, 24 Aug 2012 08:30:29 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Fri, 24 Aug 2012 01:31:32 -0700 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 24 Aug 2012 01:24:20 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 24 Aug 2012 01:24:20 -0700 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.264.0; Fri, 24 Aug 2012 01:30:17 -0700 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw02.nvidia.com with MailMarshal (v6,7,2,8378) id ; Fri, 24 Aug 2012 01:31:08 -0700 Received: from oreo.Nvidia.com (dhcp-10-21-25-186.nvidia.com [10.21.25.186]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id q7O8TWB1024274; Fri, 24 Aug 2012 01:30:13 -0700 (PDT) From: Hiroshi Doyu To: Date: Fri, 24 Aug 2012 11:29:05 +0300 Message-ID: <1345796945-21115-5-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com> References: <1345796945-21115-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 Cc: linux@arm.linux.org.uk, arnd@arndb.de, konrad.wilk@oracle.com, minchan@kernel.org, linux-kernel@vger.kernel.org, linaro-mm-sig@lists.linaro.org, linux-mm@kvack.org, kyungmin.park@samsung.com, pullip.cho@samsung.com, linux-arm-kernel@lists.infradead.org Subject: [Linaro-mm-sig] [v3 4/4] ARM: dma-mapping: IOMMU allocates pages from atomic_pool with GFP_ATOMIC X-BeenThere: linaro-mm-sig@lists.linaro.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: "Unified memory management interest group." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linaro-mm-sig-bounces@lists.linaro.org Errors-To: linaro-mm-sig-bounces@lists.linaro.org X-Gm-Message-State: ALoCoQk7dH8SWnt4fNLZrvZa1Hs1dpI3Lb7sCzH8P1WjE1DFe9+LQ641nlP0dZJxWZ5IXRYGxZoi Make use of the same atomic pool as DMA does, and skip a kernel page mapping which can involve sleep'able operations at allocating a kernel page table. Signed-off-by: Hiroshi Doyu --- arch/arm/mm/dma-mapping.c | 36 ++++++++++++++++++++++++++++++++++++ 1 files changed, 36 insertions(+), 0 deletions(-) diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 58a852b..3ce152a 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -1205,6 +1205,34 @@ static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) return NULL; } +static void *__iommu_alloc_atomic(struct device *dev, size_t size, + dma_addr_t *handle) +{ + struct page *page; + void *addr; + + addr = __alloc_from_pool(size, &page); + if (!addr) + return NULL; + + *handle = __iommu_create_mapping(dev, &page, size); + if (*handle == DMA_ERROR_CODE) + goto err_mapping; + + return addr; + +err_mapping: + __free_from_pool(addr, size); + return NULL; +} + +static void __iommu_free_atomic(struct device *dev, struct page **pages, + dma_addr_t handle, size_t size) +{ + __iommu_remove_mapping(dev, handle, size); + __free_from_pool(page_address(pages[0]), size); +} + static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) { @@ -1215,6 +1243,9 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, *handle = DMA_ERROR_CODE; size = PAGE_ALIGN(size); + if (gfp & GFP_ATOMIC) + return __iommu_alloc_atomic(dev, size, handle); + pages = __iommu_alloc_buffer(dev, size, gfp); if (!pages) return NULL; @@ -1281,6 +1312,11 @@ void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, return; } + if (__in_atomic_pool(cpu_addr, size)) { + __iommu_free_atomic(dev, pages, handle, size); + return; + } + if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) { unmap_kernel_range((unsigned long)cpu_addr, size); vunmap(cpu_addr);