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Thu, 29 May 2025 18:50:15 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 29 May 2025 18:50:15 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 29 May 2025 18:50:15 -0400 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 54TMnubA017159; Thu, 29 May 2025 18:49:58 -0400 From: Jonathan Santos To: , , , , CC: Sergiu Cuciurean , , , , , , , , , , , , , , , , , , , Bartosz Golaszewski , Jonathan Santos Subject: [PATCH v9 07/12] iio: adc: ad7768-1: Add GPIO controller support Date: Thu, 29 May 2025 19:49:55 -0300 Message-ID: <10727763985bce4249219bb68bab3c0f2f9db978.1748447035.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Authority-Analysis: v=2.4 cv=CccI5Krl c=1 sm=1 tr=0 ts=6838e4a9 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=dt9VzEwgFbYA:10 a=gAnH3GRIAAAA:8 a=KKAkSRfTAAAA:8 a=ItmwtGPuVRerelARzv0A:9 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: Y1BNJxD-2S6H_1X6E2GGRoxDSrX_0_yW X-Proofpoint-GUID: Y1BNJxD-2S6H_1X6E2GGRoxDSrX_0_yW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI5MDIyMiBTYWx0ZWRfX71g3FtBMeL6w 7oZOur7eGPCJoT7V6AMNjfsfnPngsnlKm4gVd3PopAltlSnzU+gfvdm60sQyjGmj4bEaPjR/1l8 EYlGb+XTFc5zv9LgB1AkAJzmRZ63DvOYOUC6V0XvEHEVBmCpv/U0We+1GjCixmGQmfj6qZ985pI EQZnxCOmDUwWBTlGqYzClw3JwPlj8Zfwae1jfCIjq29cV85eRp98xt0LGUI6m2PFoBK4m9eyJ5M mD9F6VZIZtYnz21KPbHGgpmSGm2zj+1w2ScjrFfkYD+2rx0pGm7BP+xvCTQueNqu1QaZQjepvXF +MTsgqv4XdptBkIN5ZcTF+jZThcSGLJtP9ZErV4X1UV0OO6QYQBo5AAj0b7imeLzPDwa1f+cA/U Z+NWQPwxObfFoOkrioTTEzd5HMpSzchjF2K+1SnfhQvVGh5Gf1ddQqmObuG8mzuc5UtxSlv9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-29_10,2025-05-29_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 bulkscore=0 spamscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505290222 From: Sergiu Cuciurean The AD7768-1 has the ability to control other local hardware (such as gain stages),to power down other blocks in the signal chain, or read local status signals over the SPI interface. Add direct mode conditional locks in the gpio callbacks to prevent register access when the device is in buffered mode. This change exports the AD7768-1's four gpios and makes them accessible at an upper layer. Reviewed-by: Marcelo Schmitt Acked-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Signed-off-by: Sergiu Cuciurean Co-developed-by: Jonathan Santos Signed-off-by: Jonathan Santos --- v9 Changes: * None. v8 Changes: * None. v7 Changes: * moved gpiochip field in the ad7768_state struct. * replaced regmap_update_bits() for regmap_assign_bits() in the gpio_set() function. * other nits. * removed gpio.h header. v6 Changes: * Replaced deprecated .set callback with .set_rv. v5 Changes: * Use the new new iio_device_claim/release_direct() functions. * replaced gpiochip_add_data() for devm_gpiochip_add_data(). v4 Changes: * Mentioned in the commit message that we cannot tweak the GPIO controller when the device is not in direct mode. v3 Changes: * Fixed SoB order. * Added missing iio_device_release_direct_mode(). * Simplified some regmap writes. * Removed ad7768_gpio_request() callback. * Fixed line wrapping. v2 Changes: * Replaced mutex for iio_device_claim_direct_mode(). * Use gpio-controller property to conditionally enable the GPIO support. * OBS: when the GPIO is configured as output, we should read the current state value from AD7768_REG_GPIO_WRITE. --- drivers/iio/adc/ad7768-1.c | 140 ++++++++++++++++++++++++++++++++++++- 1 file changed, 138 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index cd5ce774df72..d0366d570c14 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -88,6 +89,16 @@ #define AD7768_REG_ANALOG2_VCM_MSK GENMASK(2, 0) #define AD7768_REG_ANALOG2_VCM(x) FIELD_PREP(AD7768_REG_ANALOG2_VCM_MSK, (x)) +/* AD7768_REG_GPIO_CONTROL */ +#define AD7768_GPIO_UNIVERSAL_EN BIT(7) +#define AD7768_GPIO_CONTROL_MSK GENMASK(3, 0) + +/* AD7768_REG_GPIO_WRITE */ +#define AD7768_GPIO_WRITE_MSK GENMASK(3, 0) + +/* AD7768_REG_GPIO_READ */ +#define AD7768_GPIO_READ_MSK GENMASK(3, 0) + #define AD7768_VCM_OFF 0x07 enum ad7768_conv_mode { @@ -177,6 +188,7 @@ struct ad7768_state { struct gpio_desc *gpio_sync_in; struct gpio_desc *gpio_reset; const char *labels[ARRAY_SIZE(ad7768_channels)]; + struct gpio_chip gpiochip; /* * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. @@ -355,6 +367,122 @@ static int ad7768_set_dig_fil(struct ad7768_state *st, return 0; } +static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct iio_dev *indio_dev = gpiochip_get_data(chip); + struct ad7768_state *st = iio_priv(indio_dev); + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret = regmap_clear_bits(st->regmap, AD7768_REG_GPIO_CONTROL, + BIT(offset)); + iio_device_release_direct(indio_dev); + + return ret; +} + +static int ad7768_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct iio_dev *indio_dev = gpiochip_get_data(chip); + struct ad7768_state *st = iio_priv(indio_dev); + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret = regmap_set_bits(st->regmap, AD7768_REG_GPIO_CONTROL, + BIT(offset)); + iio_device_release_direct(indio_dev); + + return ret; +} + +static int ad7768_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct iio_dev *indio_dev = gpiochip_get_data(chip); + struct ad7768_state *st = iio_priv(indio_dev); + unsigned int val; + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); + if (ret) + goto err_release; + + /* + * If the GPIO is configured as an output, read the current value from + * AD7768_REG_GPIO_WRITE. Otherwise, read the input value from + * AD7768_REG_GPIO_READ. + */ + if (val & BIT(offset)) + ret = regmap_read(st->regmap, AD7768_REG_GPIO_WRITE, &val); + else + ret = regmap_read(st->regmap, AD7768_REG_GPIO_READ, &val); + if (ret) + goto err_release; + + ret = !!(val & BIT(offset)); +err_release: + iio_device_release_direct(indio_dev); + + return ret; +} + +static int ad7768_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct iio_dev *indio_dev = gpiochip_get_data(chip); + struct ad7768_state *st = iio_priv(indio_dev); + unsigned int val; + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); + if (ret) + goto err_release; + + if (val & BIT(offset)) + ret = regmap_assign_bits(st->regmap, AD7768_REG_GPIO_WRITE, + BIT(offset), value); + +err_release: + iio_device_release_direct(indio_dev); + + return ret; +} + +static int ad7768_gpio_init(struct iio_dev *indio_dev) +{ + struct ad7768_state *st = iio_priv(indio_dev); + int ret; + + ret = regmap_write(st->regmap, AD7768_REG_GPIO_CONTROL, + AD7768_GPIO_UNIVERSAL_EN); + if (ret) + return ret; + + st->gpiochip = (struct gpio_chip) { + .label = "ad7768_1_gpios", + .base = -1, + .ngpio = 4, + .parent = &st->spi->dev, + .can_sleep = true, + .direction_input = ad7768_gpio_direction_input, + .direction_output = ad7768_gpio_direction_output, + .get = ad7768_gpio_get, + .set_rv = ad7768_gpio_set, + .owner = THIS_MODULE, + }; + + return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev); +} + static int ad7768_set_freq(struct ad7768_state *st, unsigned int freq) { @@ -496,8 +624,9 @@ static const struct iio_info ad7768_info = { .debugfs_reg_access = &ad7768_reg_access, }; -static int ad7768_setup(struct ad7768_state *st) +static int ad7768_setup(struct iio_dev *indio_dev) { + struct ad7768_state *st = iio_priv(indio_dev); int ret; st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset", @@ -530,6 +659,13 @@ static int ad7768_setup(struct ad7768_state *st) if (IS_ERR(st->gpio_sync_in)) return PTR_ERR(st->gpio_sync_in); + /* Only create a Chip GPIO if flagged for it */ + if (device_property_read_bool(&st->spi->dev, "gpio-controller")) { + ret = ad7768_gpio_init(indio_dev); + if (ret) + return ret; + } + /* Set the default sampling frequency to 32000 kSPS */ return ad7768_set_freq(st, 32000); } @@ -869,7 +1005,7 @@ static int ad7768_probe(struct spi_device *spi) if (ret) return ret; - ret = ad7768_setup(st); + ret = ad7768_setup(indio_dev); if (ret < 0) { dev_err(&spi->dev, "AD7768 setup failed\n"); return ret;