From patchwork Fri Jun 23 14:58:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 106268 Delivered-To: patch@linaro.org Received: by 10.140.91.2 with SMTP id y2csp251883qgd; Fri, 23 Jun 2017 07:59:12 -0700 (PDT) X-Received: by 10.98.72.201 with SMTP id q70mr1535395pfi.23.1498229952340; Fri, 23 Jun 2017 07:59:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498229952; cv=none; d=google.com; s=arc-20160816; b=W/OsIvELFT3WG0+PyJyf9060ZzsOofhNiIlO09Rp+BduTpVi1jb7CXW3rNUqZ8SmcR 05Jjzn0S2nR1aXO+FK2I8ZeB2eZPpXSRMooLf+zrhcP+CyyqcACka/qkPkoR2V08WbT4 /Kt/MHk/hmUmGfRvAzrAaRCK2YCY3X2508j/bjaURjVH8xYNTVZ9aU2P1nQCcv+gSVWP 32EotIxdrLn+trmxkPFf7i1WpNZKxdMGLLe6a2eVR4HerAjE8aH/008DpEXL64bA5gMR 8m9uYRvrsJkJ2+Orkjv1xlofxzVPYjzHK3lbfNiOD6uRsLk0liu1VQ2jPgOTxsXNmcYV eRBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=W31SLF1wlS2fIynPt7++0iKaFtDhWb9dQtVwjm8M19U=; b=DbReZOlij/jVilAxquxuIDjHKlDT9tY3IcY7APlilMsSwg81FUPH0yk6VTbFmMm3c0 JOHXjcZzOmER2RUsiAKCrgLCQCPn/cxlrvwkFbYzZGplVbPWm7Bjbf8pm6TLSRRe33Yj 0l9OnIXIVq1onyQsAGeG86b7gn0CGj4f9aoNy60HhqME6wewlYekoM7AsUWCDfMoBeRU 1DQZdMdUv4RG6S1jBoF5Svt5kyjz+pNgADmZU0w3S6lkQ37uVPbQbOjnJ6bOZREMn0m+ fFBJJiYVBL5e17ZVx7xn7U+jr+zfbWhwQNZtMHeyqHNgQ9uYw9gFhA9WWz99tCs1EGU5 p83w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p11si3597830pgn.190.2017.06.23.07.59.12; Fri, 23 Jun 2017 07:59:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754421AbdFWO7L (ORCPT + 8 others); Fri, 23 Jun 2017 10:59:11 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:8787 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754418AbdFWO7L (ORCPT ); Fri, 23 Jun 2017 10:59:11 -0400 Received: from 172.30.72.55 (EHLO DGGEML402-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AQV92878; Fri, 23 Jun 2017 22:59:08 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEML402-HUB.china.huawei.com (10.3.17.38) with Microsoft SMTP Server id 14.3.301.0; Fri, 23 Jun 2017 22:59:00 +0800 From: shameer To: , , , , , CC: , , , , , , , , , shameer Subject: [PATCH v3 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Date: Fri, 23 Jun 2017 15:58:01 +0100 Message-ID: <20170623145801.325244-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170623145801.325244-1-shameerali.kolothum.thodi@huawei.com> References: <20170623145801.325244-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.594D2CBD.0014, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: f9c2803f2005d7378305baa35f391a70 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. Signed-off-by: shameer --- drivers/iommu/arm-smmu-v3.c | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index abe4b88..c9346f2 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -597,6 +597,7 @@ struct arm_smmu_device { u32 features; #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) +#define ARM_SMMU_OPT_RESV_HW_MSI (1 << 1) u32 options; struct arm_smmu_cmdq cmdq; @@ -1904,14 +1905,34 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { struct iommu_resv_region *region; + struct arm_smmu_device *smmu; + struct iommu_fwspec *fwspec = dev->iommu_fwspec; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + int resv = 0; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); - if (!region) + smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); + if (WARN_ON(!smmu)) return; - list_add_tail(®ion->list, head); + if ((smmu->options & ARM_SMMU_OPT_RESV_HW_MSI)) { + + if (!is_of_node(smmu->dev->fwnode)) + resv = iort_iommu_its_get_resv_regions(dev, head); + + if (resv < 0) { + dev_warn(dev, "HW MSI region resv failed: %d\n", resv); + return; + } + } + + if (!resv) { + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); + if (!region) + return; + + list_add_tail(®ion->list, head); + } iommu_dma_get_resv_regions(dev, head); } @@ -2611,6 +2632,7 @@ static void parse_driver_acpi_options(struct acpi_iort_smmu_v3 *iort_smmu, switch (iort_smmu->model) { case ACPI_IORT_SMMU_HISILICON_HI161X: smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; break; default: break;