From patchwork Wed Sep 27 13:32:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 114369 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5050359qgf; Wed, 27 Sep 2017 06:35:12 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBOAJUiNGqKbFt2sMOXv7OyRICYu1rpgyGZPqS3XK10o7u5gdDNazE4xsx+NYxOTffBj6/X X-Received: by 10.99.114.29 with SMTP id n29mr1386665pgc.258.1506519311929; Wed, 27 Sep 2017 06:35:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506519311; cv=none; d=google.com; s=arc-20160816; b=rPcdHxU+9Q6XavZiiZ0I7hGOg/eg7kzsMkLkSyoZi5pZvmSpJf5iYHKzgEu0ogCtDe /U2QOqQT79RReoMux9GrOmcm6ugkmXFHkxiFNjl4Kinbsrrfl8GdvuN7hmttnaBzWI2z lxY5nlZoasXmvDwSqN+X0mwMk2cSI3t4phA6c4cXg+IYd4/bsuDvo+6OL3KytR5pWBfI j8kFdha+2nRYmtJPN8buoBRup3J8UyBtGv3qa0McCvn+e9cBg43OYOQtU3SZzY+whib9 zVKYeY4mrdzn01OJ7wbiP8wxv4nmDjaaxMeskBRAB9esJe7cVUlMn0lq0cHTu29irIs9 a5GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=7PuMzhE73aZd2IdlVFjvki7Zu7txRoSGuoDnIMfnFTE=; b=vYJ6OODw7Hps6ApaX8LJRfegx3W/u2OsT6xG2mSsL/b3GjJz9SLKHXuf3SudxSOV6U Lfw/A7nkmz4KxwsLdJKTZ4DnWO6KUpMcQ3LbLY1b9PQdRI963kTATAfzdZNR9cCvvSEZ WASy3LC7Vg+L5FXrarB+yZtXAx6B79PwMy9kXSAVA4Tb8xKm1sqVJd2J+/v6I1kE6UfL Ke+hiCOuvzu2QHoOKDL6Hy1hZ0D75UFlPwvXqbI4wlpkW49swoiy/RuTafwU9ZV5R3bC HHfmA7t3ATB477gWtmmM8m3tzrynataR4yZLmy0pj00IBM9eJcInd6uiahmJE3Xf2M/T k/5w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u9si7660961pge.139.2017.09.27.06.35.11; Wed, 27 Sep 2017 06:35:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751926AbdI0NfK (ORCPT + 7 others); Wed, 27 Sep 2017 09:35:10 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:7449 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751959AbdI0NfK (ORCPT ); Wed, 27 Sep 2017 09:35:10 -0400 Received: from 172.30.72.58 (EHLO DGGEMS401-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIB16842; Wed, 27 Sep 2017 21:35:06 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.301.0; Wed, 27 Sep 2017 21:34:58 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , , Shameer Kolothum Subject: [PATCH v8 1/5] Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon erratum 161010801 Date: Wed, 27 Sep 2017 14:32:37 +0100 Message-ID: <20170927133241.21036-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170927133241.21036-1-shameerali.kolothum.thodi@huawei.com> References: <20170927133241.21036-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.59CBA90A.015A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 1199e1a103f72e2595b31297b988f396 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org From: John Garry The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms hip06/hip07 to support the SMMU mappings for MSI transactions. On these platforms, GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch adds a compatible string to implement this errata for HiSilicon Hi161x SMMUv3 model on hip06/hip07 platforms. Also, the arm64 silicon errata is updated with this same erratum. Signed-off-by: John Garry [Shameer: Modified to use compatible string for errata] Signed-off-by: Shameer Kolothum --- Documentation/arm64/silicon-errata.txt | 1 + Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 66e8ce1..02816b1 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -70,6 +70,7 @@ stable kernels. | | | | | | Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 | | Hisilicon | Hip0{6,7} | #161010701 | N/A | +| Hisilicon | Hip0{6,7} | #161010801 | N/A | | | | | | | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt index c9abbf3..3b0d599 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt @@ -7,11 +7,18 @@ the PCIe specification. ** SMMUv3 required properties: -- compatible : Should include: +- compatible : Should be one of: + + "arm,smmu-v3" + "hisilicon,hi161x-smmu-v3" + + depending on the particular implementation. * "arm,smmu-v3" for any SMMUv3 compliant implementation. This entry should be last in the compatible list. + * "hisilicon,hi161x-smmu-v3" for HiSilicon hi161x + SMMUv3 implementation on hip06/hip07 platforms. - reg : Base address and size of the SMMU.