From patchwork Thu Nov 19 12:11:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 328406 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp361532ils; Thu, 19 Nov 2020 04:13:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJxIQxjwkpjkMS6Dmpe1CcVJ7lo/tLbhxr2MyZwGCmnYFXuzgtDLPQCeSsLOQPLfqZmZL4I3 X-Received: by 2002:a17:906:cd0f:: with SMTP id oz15mr28611219ejb.200.1605788034450; Thu, 19 Nov 2020 04:13:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605788034; cv=none; d=google.com; s=arc-20160816; b=ULFgffZ4ibZF8mLb8XUqFr/PXUD8lzaurzk9fjCt9Kl/8HepYiBmBzptBQ46VVFQP7 n/HORFOGvTvymVRNU1bWxiQCc4GURdNJSfFIZCVBJ6Chm4lRPtl7sWs6/1Z1apff1Pxw tkxPd3qeTu2wsbFhECN1xOauRl0Kebln7vdq1tIoEeVpcRw4vo4Q7ujuRUu2gh89ehxU bZFQXZDbX3nkcNM+T5B9zeTC2hxdA4HF1h0H/FoXSsP8CbqtUfH84MQUceb11OsBwHdL 1BFjRpHfYi0dpubcP4CsZPdI29RFlRE7vRGhGXCnk+t0+0XFP0fvjZwaNK8Om2vQzZ4O QttA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=MtsW3hwrSeBC+zOFPeyA8GURRuY80bNDOvM6SFgSL0g=; b=IuE+yLfr1jhGfaJfjhj77QlpaC1Z2NaLMDWE/53THDkrF+wChJINIWG++fGkOLVfxg BtVL1PgGSipSA7RNHKsaIsMHuLZGwc64W36X20hwF3KYXPbj1GrGZZRpWXklLwfsTjgC Aqv8Y19PwLCJiA9CEzVmhlc8px1+pqidRb31x8eq+1Ep1lc/hDCeJC8uPgCrGSs407nk AjEo5IqwGBVnBIi9q9qCH23Y5yzv7WKCd1+9zJsuw2YCtOBw1VW6WR9XsJs0lHEtOFvA jwln0ChvQhVOc0Vryb7SGzN2K7v5k0uppQ6JYQUUKeDDJtcbQNIXQQd3P6Nzo73Y7Ylk vw8g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id qc4si16705640ejb.188.2020.11.19.04.13.54; Thu, 19 Nov 2020 04:13:54 -0800 (PST) Received-SPF: pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727268AbgKSMNI (ORCPT + 5 others); Thu, 19 Nov 2020 07:13:08 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:7954 "EHLO szxga06-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726691AbgKSMNH (ORCPT ); Thu, 19 Nov 2020 07:13:07 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4CcJTz013FzhdPH; Thu, 19 Nov 2020 20:12:55 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.210.168.73) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.487.0; Thu, 19 Nov 2020 20:12:56 +0800 From: Shameer Kolothum To: , , , CC: , , , , , , , , Subject: [RFC PATCH v2 6/8] =?utf-8?q?iommu/arm-smmu-v3=3A_Add_bypass_flag?= =?utf-8?b?IHRvwqBhcm1fc21tdV93cml0ZV9zdHJ0YWJfZW50KCk=?= Date: Thu, 19 Nov 2020 12:11:48 +0000 Message-ID: <20201119121150.3316-7-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20201119121150.3316-1-shameerali.kolothum.thodi@huawei.com> References: <20201119121150.3316-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.210.168.73] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org By default, disable_bypass is set and any dev without an iommu domain installs STE with CFG_ABORT during arm_smmu_init_bypass_stes(). Introduce a "bypass" flag to arm_smmu_write_strtab_ent() so that we can force it to install CFG_BYPASS STE for specific SIDs. This will be useful for RMR related SIDs. Signed-off-by: Shameer Kolothum --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 1953b317d814..5f366d5a9ebf 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1174,7 +1174,7 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) } static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, - __le64 *dst) + __le64 *dst, bool bypass) { /* * This is hideously complicated, but we only really care about @@ -1245,7 +1245,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, /* Bypass/fault */ if (!smmu_domain || !(s1_cfg || s2_cfg)) { - if (!smmu_domain && disable_bypass) + if (!smmu_domain && disable_bypass && !bypass) val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); else val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS); @@ -1317,7 +1317,7 @@ static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent) unsigned int i; for (i = 0; i < nent; ++i) { - arm_smmu_write_strtab_ent(NULL, -1, strtab); + arm_smmu_write_strtab_ent(NULL, -1, strtab, false); strtab += STRTAB_STE_DWORDS; } } @@ -2038,7 +2038,7 @@ static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master) if (j < i) continue; - arm_smmu_write_strtab_ent(master, sid, step); + arm_smmu_write_strtab_ent(master, sid, step, false); } }