From patchwork Mon Aug 8 08:30:04 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 3293 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 98E2E2406F for ; Mon, 8 Aug 2011 08:30:24 +0000 (UTC) Received: from mail-qy0-f173.google.com (mail-qy0-f173.google.com [209.85.216.173]) by fiordland.canonical.com (Postfix) with ESMTP id 3A0CFA1802E for ; Mon, 8 Aug 2011 08:30:24 +0000 (UTC) Received: by qyk31 with SMTP id 31so1621503qyk.11 for ; Mon, 08 Aug 2011 01:30:23 -0700 (PDT) Received: by 10.229.44.195 with SMTP id b3mr4058116qcf.7.1312792223604; Mon, 08 Aug 2011 01:30:23 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.229.190.71 with SMTP id dh7cs6642qcb; Mon, 8 Aug 2011 01:30:23 -0700 (PDT) Received: from mr.google.com ([10.220.180.194]) by 10.220.180.194 with SMTP id bv2mr1234347vcb.7.1312792223201 (num_hops = 1); Mon, 08 Aug 2011 01:30:23 -0700 (PDT) Received: by 10.220.180.194 with SMTP id bv2mr997276vcb.7.1312792221933; Mon, 08 Aug 2011 01:30:21 -0700 (PDT) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe001.messaging.microsoft.com [216.32.181.181]) by mx.google.com with ESMTPS id bv9si2917294vcb.23.2011.08.08.01.30.19 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 08 Aug 2011 01:30:20 -0700 (PDT) Received-SPF: neutral (google.com: 216.32.181.181 is neither permitted nor denied by best guess record for domain of richard.zhu@linaro.org) client-ip=216.32.181.181; Authentication-Results: mx.google.com; spf=neutral (google.com: 216.32.181.181 is neither permitted nor denied by best guess record for domain of richard.zhu@linaro.org) smtp.mail=richard.zhu@linaro.org Received: from mail215-ch1-R.bigfish.com (216.32.181.174) by CH1EHSOBE016.bigfish.com (10.43.70.66) with Microsoft SMTP Server id 14.1.225.22; Mon, 8 Aug 2011 08:30:18 +0000 Received: from mail215-ch1 (localhost.localdomain [127.0.0.1]) by mail215-ch1-R.bigfish.com (Postfix) with ESMTP id CC0DF128021B; Mon, 8 Aug 2011 08:30:18 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail215-ch1 (localhost.localdomain [127.0.0.1]) by mail215-ch1 (MessageSwitch) id 1312792218430171_25407; Mon, 8 Aug 2011 08:30:18 +0000 (UTC) Received: from CH1EHSMHS002.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.250]) by mail215-ch1.bigfish.com (Postfix) with ESMTP id 58A34A6004E; Mon, 8 Aug 2011 08:30:18 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS002.bigfish.com (10.43.70.2) with Microsoft SMTP Server (TLS) id 14.1.225.22; Mon, 8 Aug 2011 08:30:15 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.323.2; Mon, 8 Aug 2011 03:30:14 -0500 Received: from x-VirtualBox.ap.freescale.net ([10.192.242.29]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p788U9Js021840; Mon, 8 Aug 2011 03:30:10 -0500 (CDT) From: Richard Zhu To: CC: , , , , , , , Richard Zhu Subject: [PATCH V4] mmc: Enable the ADMA2 on esdhc imx driver Date: Mon, 8 Aug 2011 16:30:04 +0800 Message-ID: <1312792204-7652-1-git-send-email-richard.zhu@linaro.org> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com Eanble the ADMA2 mode for freescale esdhc imx driver, tested on MX25 3DS board, MX51 BBG board and MX53 LOCO board. This patch is only used to enable the ADMA2 for MX51/53 platforms. MX25/35 can't support the ADMA2 mode, set BROKEN_ADMA quirk on MX25/35 platforms. The ADMA mode supported or not can be distinguished by the bit20 of Capability Register(offset 0x40) in FSL eSDHC module. Signed-off-by: Richard Zhu --- drivers/mmc/host/sdhci-esdhc-imx.c | 45 +++++++++++++++++++++++++++++++++-- 1 files changed, 42 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index e62d33f..a966d5c 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -30,6 +30,14 @@ #define SDHCI_VENDOR_SPEC 0xC0 #define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002 +/* + * There is INT DMA ERR mis-match between eSDHC and STD SDHC SPEC + * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, + * but bit28 is used as the INT DMA ERR in fsl eSDHC design. + * Define this macro DMA error INT for fsl eSDHC + */ +#define SDHCI_INT_VENDOR_SPEC_DMA_ERR 0x10000000 + #define ESDHC_FLAG_GPIO_FOR_CD (1 << 0) /* * The CMDTYPE of the CMD register (offset 0xE) should be set to @@ -79,6 +87,27 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) val |= SDHCI_CARD_PRESENT; } + if (unlikely(reg == SDHCI_CAPABILITIES)) { + /* In FSL esdhc IC module, only bit20 is used to indicate the + * ADMA2 capability of esdhc, but this bit is messed up on some + * SOCs (e.x MX25,MX35 this bit is set, but it can't support the + * ADMA2 actually). So set the BROKEN_ADMA quirk on MX25/35 + * paltforms. + */ + + if (val & SDHCI_CAN_DO_ADMA1) { + val &= ~SDHCI_CAN_DO_ADMA1; + val |= SDHCI_CAN_DO_ADMA2; + } + } + + if (unlikely(reg == SDHCI_INT_STATUS)) { + if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) { + val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR; + val |= SDHCI_INT_ADMA_ERROR; + } + } + return val; } @@ -125,6 +154,14 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) writel(v, host->ioaddr + SDHCI_VENDOR_SPEC); } + if (unlikely((reg == SDHCI_INT_ENABLE) + || (reg == SDHCI_SIGNAL_ENABLE))) { + if (val & SDHCI_INT_ADMA_ERROR) { + val &= ~SDHCI_INT_ADMA_ERROR; + val |= SDHCI_INT_VENDOR_SPEC_DMA_ERR; + } + } + writel(val, host->ioaddr + reg); } @@ -225,9 +262,10 @@ static struct sdhci_ops sdhci_esdhc_ops = { }; static struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { - .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_ADMA + .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT + | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC + | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | SDHCI_QUIRK_BROKEN_CARD_DETECTION, - /* ADMA has issues. Might be fixable */ .ops = &sdhci_esdhc_ops, }; @@ -284,7 +322,8 @@ static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev) if (cpu_is_mx25() || cpu_is_mx35()) { /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ - host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK; + host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK + | SDHCI_QUIRK_BROKEN_ADMA; /* write_protect can't be routed to controller, use gpio */ sdhci_esdhc_ops.get_ro = esdhc_pltfm_get_ro; }