From patchwork Tue Aug 9 19:41:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 3325 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 6BB8A2406C for ; Tue, 9 Aug 2011 19:41:43 +0000 (UTC) Received: from mail-qw0-f52.google.com (mail-qw0-f52.google.com [209.85.216.52]) by fiordland.canonical.com (Postfix) with ESMTP id 34AF8A18416 for ; Tue, 9 Aug 2011 19:41:43 +0000 (UTC) Received: by qwb8 with SMTP id 8so279372qwb.11 for ; Tue, 09 Aug 2011 12:41:42 -0700 (PDT) Received: by 10.229.159.194 with SMTP id k2mr2304370qcx.83.1312918902651; Tue, 09 Aug 2011 12:41:42 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.229.190.71 with SMTP id dh7cs57327qcb; Tue, 9 Aug 2011 12:41:40 -0700 (PDT) Received: from mr.google.com ([10.213.3.155]) by 10.213.3.155 with SMTP id 27mr2241964ebn.18.1312918900070 (num_hops = 1); Tue, 09 Aug 2011 12:41:40 -0700 (PDT) Received: by 10.213.3.155 with SMTP id 27mr1663196ebn.18.1312918899148; Tue, 09 Aug 2011 12:41:39 -0700 (PDT) Received: from eu1sys200aog118.obsmtp.com (eu1sys200aog118.obsmtp.com [207.126.144.145]) by mx.google.com with SMTP id x18si198549eej.76.2011.08.09.12.41.34 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 09 Aug 2011 12:41:39 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.145 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.145; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.145 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob118.postini.com ([207.126.147.11]) with SMTP ID DSNKTkGNbqRQRrjM1pjkoFhGMR9bZ6ugIpEn@postini.com; Tue, 09 Aug 2011 19:41:38 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 17C26A2; Tue, 9 Aug 2011 19:41:33 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C6C5F252E; Tue, 9 Aug 2011 19:41:33 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 749D524C2AB; Tue, 9 Aug 2011 21:41:23 +0200 (CEST) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 9 Aug 2011 21:41:33 +0200 From: Linus Walleij To: Cc: Lee Jones , Linus Walleij Subject: [PATCH 2/5] mach-u300: drop SEMI config option Date: Tue, 9 Aug 2011 21:41:31 +0200 Message-ID: <1312918891-11861-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Linus Walleij When we have only dual-RAM configurations, the SEMI (shared memory interface) must always be enabled. Signed-off-by: Linus Walleij --- arch/arm/mach-u300/Kconfig | 8 -------- arch/arm/mach-u300/core.c | 9 +-------- 2 files changed, 1 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig index d3a9ca4..966a5a0 100644 --- a/arch/arm/mach-u300/Kconfig +++ b/arch/arm/mach-u300/Kconfig @@ -54,14 +54,6 @@ config U300_DEBUG help Debug support for U300 in sysfs, procfs etc. -config MACH_U300_SEMI_IS_SHARED - bool "The SEMI is used by both the access and application side" - depends on MACH_U300 - help - This makes it possible to use the SEMI (Shared External - Memory Interface) from both from access and application - side. - config MACH_U300_SPIDUMMY bool "SSP/SPI dummy chip" select SPI diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 399c89f..8b78af9 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -1837,17 +1837,10 @@ void __init u300_init_devices(void) /* Register subdevices on the SPI bus */ u300_spi_register_board_devices(); -#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED - /* - * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when - * both subsystems are requesting this mode. - * If we not share the Acc SDRAM, this is never the case. Therefore - * enable it here from the App side. - */ + /* Enable SEMI self refresh */ val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) | U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE; writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR); -#endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */ } static int core_module_init(void)