From patchwork Wed Aug 24 09:23:55 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 3646 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id A2DD223F4D for ; Wed, 24 Aug 2011 09:24:06 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 8F63FA18916 for ; Wed, 24 Aug 2011 09:24:06 +0000 (UTC) Received: by mail-bw0-f52.google.com with SMTP id zs2so1150659bkb.11 for ; Wed, 24 Aug 2011 02:24:06 -0700 (PDT) Received: by 10.204.133.17 with SMTP id d17mr2197700bkt.122.1314177846320; Wed, 24 Aug 2011 02:24:06 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.204.41.75 with SMTP id n11cs7297bke; Wed, 24 Aug 2011 02:24:06 -0700 (PDT) Received: by 10.14.7.148 with SMTP id 20mr126040eep.245.1314177845774; Wed, 24 Aug 2011 02:24:05 -0700 (PDT) Received: from eu1sys200aog115.obsmtp.com (eu1sys200aog115.obsmtp.com [207.126.144.139]) by mx.google.com with SMTP id e14si687119eea.41.2011.08.24.02.24.01 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 24 Aug 2011 02:24:05 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.139 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.139; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.139 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob115.postini.com ([207.126.147.11]) with SMTP ID DSNKTlTDMULgKYxVyXpNhwc1ZGjaRxbETBdx@postini.com; Wed, 24 Aug 2011 09:24:05 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 4434B68; Wed, 24 Aug 2011 09:24:00 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id CE9FB4E; Wed, 24 Aug 2011 09:23:59 +0000 (GMT) Received: from exdcvycastm022.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm022", Issuer "exdcvycastm022" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 689B2A807B; Wed, 24 Aug 2011 11:23:55 +0200 (CEST) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.30) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 24 Aug 2011 11:23:58 +0200 From: Linus Walleij To: Cc: Lee Jones , Linus Walleij , Srinidhi Kasagar , Rabin Vincent Subject: [PATCH 3/3] mach-ux500: unlock I&D l2x0 caches before init Date: Wed, 24 Aug 2011 11:23:55 +0200 Message-ID: <1314177835-19186-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Linus Walleij Apparently U8500 U-Boot versions may leave the l2x0 locked down before executing the kernel. Make sure we unlock it before we initialize the l2x0. Cc: Srinidhi Kasagar Cc: Rabin Vincent Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/cache-l2x0.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index aa2d77f..f5c31f1 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -59,6 +59,16 @@ static int ux500_l2x0_init(void) else ux500_unknown_soc(); + /* + * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions + * apparently locks both caches before jumping to the kernel. + */ + if (readl_relaxed(l2x0_base + L2X0_LOCKDOWN_WAY_D) & 0xFF) + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D); + + if (readl_relaxed(l2x0_base + L2X0_LOCKDOWN_WAY_I) & 0xFF) + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I); + /* 64KB way size, 8 way associativity, force WA */ l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);