From patchwork Thu Sep 22 13:46:32 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 4268 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 7FF4323EFA for ; Thu, 22 Sep 2011 13:47:10 +0000 (UTC) Received: from mail-ey0-f180.google.com (mail-ey0-f180.google.com [209.85.215.180]) by fiordland.canonical.com (Postfix) with ESMTP id 72CE2A1810C for ; Thu, 22 Sep 2011 13:47:10 +0000 (UTC) Received: by eyb6 with SMTP id 6so2139509eyb.11 for ; Thu, 22 Sep 2011 06:47:10 -0700 (PDT) Received: by 10.223.94.134 with SMTP id z6mr3108628fam.8.1316699230125; Thu, 22 Sep 2011 06:47:10 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.18.198 with SMTP id y6cs169015lad; Thu, 22 Sep 2011 06:47:09 -0700 (PDT) Received: by 10.213.15.76 with SMTP id j12mr1298829eba.9.1316699229597; Thu, 22 Sep 2011 06:47:09 -0700 (PDT) Received: from eu1sys200aog118.obsmtp.com (eu1sys200aog118.obsmtp.com. [207.126.144.145]) by mx.google.com with SMTP id x2si1527649eef.19.2011.09.22.06.46.43 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 22 Sep 2011 06:47:09 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.145 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.145; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.145 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob118.postini.com ([207.126.147.11]) with SMTP ID DSNKTns8Ql8OeY2QHPUUgnefY0VW1LW6FATj@postini.com; Thu, 22 Sep 2011 13:47:08 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id CEC40EF; Thu, 22 Sep 2011 13:38:06 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 0A91BD07; Thu, 22 Sep 2011 13:46:36 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id A614CA8065; Thu, 22 Sep 2011 15:46:29 +0200 (CEST) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Thu, 22 Sep 2011 15:46:34 +0200 From: Linus Walleij To: Cc: Lee Jones , Mattias Wallin , Thomas Gleixner , Mattias Wallin , Jonas Aaberg , Linus Walleij Subject: [PATCH 3/7] ARM: ux500: add support for clocksource DBX500 PRCMU Date: Thu, 22 Sep 2011 15:46:32 +0200 Message-ID: <1316699192-21326-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Mattias Wallin This patch adds support for the DBX500 PRCMU clocksource to ux500 platforms. Cc: Thomas Gleixner Signed-off-by: Mattias Wallin Signed-off-by: Jonas Aaberg Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/cpu.c | 9 +++++++++ arch/arm/mach-ux500/include/mach/db5500-regs.h | 2 ++ arch/arm/mach-ux500/include/mach/db8500-regs.h | 3 +++ 3 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 1da23bb..c0e4593 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -140,7 +141,15 @@ static void __init ux500_timer_init(void) else ux500_unknown_soc(); + if (cpu_is_u8500()) + clksrc_dbx500_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); + else if (cpu_is_u5500()) + clksrc_dbx500_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE); + else + ux500_unknown_soc(); + nmdk_timer_init(); + clksrc_dbx500_prcmu_init(); } struct sys_timer ux500_timer = { diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h index 6ad9832..994b5fe 100644 --- a/arch/arm/mach-ux500/include/mach/db5500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h @@ -61,6 +61,8 @@ #define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000) #define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000) #define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000) +#define U5500_PRCMU_TIMER_3_BASE (U5500_PER4_BASE + 0x07338) +#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450) #define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000) #define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000) #define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000) diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h index 0499971..751b0e6 100644 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h @@ -102,10 +102,13 @@ #define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) #define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) +#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338) +#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450) #define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000) #define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) #define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000) + /* per3 base addresses */ #define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) #define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)