From patchwork Tue Dec 13 11:24:57 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 5628 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 853BC23E11 for ; Tue, 13 Dec 2011 11:25:34 +0000 (UTC) Received: from mail-bw0-f52.google.com (mail-bw0-f52.google.com [209.85.214.52]) by fiordland.canonical.com (Postfix) with ESMTP id 6C450A18109 for ; Tue, 13 Dec 2011 11:25:34 +0000 (UTC) Received: by bke17 with SMTP id 17so9005876bke.11 for ; Tue, 13 Dec 2011 03:25:34 -0800 (PST) Received: by 10.205.120.135 with SMTP id fy7mr7581811bkc.54.1323775533965; Tue, 13 Dec 2011 03:25:33 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.205.129.2 with SMTP id hg2cs77441bkc; Tue, 13 Dec 2011 03:25:33 -0800 (PST) Received: by 10.204.145.81 with SMTP id c17mr12531189bkv.132.1323775532246; Tue, 13 Dec 2011 03:25:32 -0800 (PST) Received: from eu1sys200aog113.obsmtp.com (eu1sys200aog113.obsmtp.com. [207.126.144.135]) by mx.google.com with SMTP id b9si11424502eei.108.2011.12.13.03.25.23 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 13 Dec 2011 03:25:31 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.135 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.135; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.135 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob113.postini.com ([207.126.147.11]) with SMTP ID DSNKTuc2Gw3HtMrFGsvRpXWxoujFkNsly1VX@postini.com; Tue, 13 Dec 2011 11:25:31 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id AC29C3C; Tue, 13 Dec 2011 11:25:03 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id A256D62; Tue, 13 Dec 2011 10:57:56 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 9C25EA8065; Tue, 13 Dec 2011 12:24:59 +0100 (CET) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 13 Dec 2011 12:25:03 +0100 From: Linus Walleij To: Russell King , Cc: Colin Cross , Thomas Gleixner , Rob Herring , Santosh Shilimkar , Linus Walleij , Russell King Subject: [PATCH 3/4 v2] ARM: smp_twd: get the rate from a clock Date: Tue, 13 Dec 2011 12:24:57 +0100 Message-ID: <1323775497-28218-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Linus Walleij This break-out from Colin Cross' cpufreq-aware TWD patch will optionally retrieve the clock rate of the TWD from an external clock. A variant of this patch has been proposed by Rob Herring as well. The basic idea is to avoid recalibrating the rate of the clock at boot if the platform already know what rate the clock to the TWD block has. ChangeLog v1->v2: added clk_[prepare|unprepare] calls. Signed-off-by: Colin Cross Cc: Russell King Acked-by: Thomas Gleixner Acked-by: Rob Herring Acked-by: Santosh Shilimkar [Broke out of larger SMP TWD patch] Signed-off-by: Linus Walleij --- arch/arm/kernel/smp_twd.c | 40 +++++++++++++++++++++++++++++++++++++++- 1 files changed, 39 insertions(+), 1 deletions(-) diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 20cce4e..8327989 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -10,8 +10,10 @@ */ #include #include +#include #include #include +#include #include #include #include @@ -26,6 +28,7 @@ /* set up by the platform code */ void __iomem *twd_base; +static struct clk *twd_clk; static unsigned long twd_timer_rate; static DEFINE_PER_CPU(struct clock_event_device *, twd_ce); @@ -142,6 +145,35 @@ static irqreturn_t twd_handler(int irq, void *dev_id) return IRQ_NONE; } +static struct clk *twd_get_clock(void) +{ + struct clk *clk; + int err; + + clk = clk_get_sys("smp_twd", NULL); + if (IS_ERR(clk)) { + pr_err("smp_twd: clock not found: %d\n", (int)PTR_ERR(clk)); + return clk; + } + + err = clk_prepare(clk); + if (err) { + pr_err("smp_twd: clock failed to prepare: %d\n", err); + clk_put(clk); + return ERR_PTR(err); + } + + err = clk_enable(clk); + if (err) { + pr_err("smp_twd: clock failed to enable: %d\n", err); + clk_unprepare(clk); + clk_put(clk); + return ERR_PTR(err); + } + + return clk; +} + /* * Setup the local clock events for a CPU. */ @@ -167,7 +199,13 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) } } - twd_calibrate_rate(); + if (!twd_clk) + twd_clk = twd_get_clock(); + + if (!IS_ERR_OR_NULL(twd_clk)) + twd_timer_rate = clk_get_rate(twd_clk); + else + twd_calibrate_rate(); clk->name = "local_timer"; clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |