From patchwork Wed Mar 14 13:05:02 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lee Jones X-Patchwork-Id: 7288 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id B6C5D23E29 for ; Wed, 14 Mar 2012 13:05:24 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 7A8D4A18746 for ; Wed, 14 Mar 2012 13:05:24 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so3119093iag.11 for ; Wed, 14 Mar 2012 06:05:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=a3yES7Mhh47FFLm25Hz6J0mNlf3gbxS75SxohH0mqVQ=; b=fYsizDEMYVCTVTMFQRdKoezLyguN2ozgJ/WyUn/94JeNqhn2NCl1fEBzh5sGBBVAgh oFsF24aqew+vUAp/XS5qCQchgFslzwcRmk8oKYzSRa2SfsZW7ILeSCGi68Ltk5xooMVs Ze71VDhSfn0/j+/RGjPyEIoxatUXfjym3rXDsoc/30KdA0avCw5eqg+FG+7AMgDNnTOv ZdCa682XQ1lFWaHjQleohAGvYk3Sb2FLNS7OZ/DEHzMxfPOQeVk7M4JdzQOBoJ9ogS1p 6mu7Gq9o56kb8+fJ/k2JdGmfLsmHveOYnQAngYVa3R3hs4swiq+PwRAZeaqj21d8SRtB 3qYA== Received: by 10.50.45.228 with SMTP id q4mr4316507igm.58.1331730324294; Wed, 14 Mar 2012 06:05:24 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.53.18 with SMTP id k18csp9547ibg; Wed, 14 Mar 2012 06:05:23 -0700 (PDT) Received: by 10.216.85.81 with SMTP id t59mr1627367wee.28.1331730321150; Wed, 14 Mar 2012 06:05:21 -0700 (PDT) Received: from mail-we0-f178.google.com (mail-we0-f178.google.com [74.125.82.178]) by mx.google.com with ESMTPS id n6si5405177wic.47.2012.03.14.06.05.20 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 14 Mar 2012 06:05:21 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of lee.jones@linaro.org) client-ip=74.125.82.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of lee.jones@linaro.org) smtp.mail=lee.jones@linaro.org Received: by mail-we0-f178.google.com with SMTP id a13so2183990wer.37 for ; Wed, 14 Mar 2012 06:05:20 -0700 (PDT) Received: by 10.180.93.4 with SMTP id cq4mr5816131wib.21.1331730320623; Wed, 14 Mar 2012 06:05:20 -0700 (PDT) Received: from localhost.localdomain (cpc1-aztw13-0-0-cust473.18-1.cable.virginmedia.com. [77.102.241.218]) by mx.google.com with ESMTPS id fi4sm11477024wib.4.2012.03.14.06.05.19 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 14 Mar 2012 06:05:19 -0700 (PDT) From: Lee Jones To: linux-arm-kernel@lists.infradead.org Cc: linus.walleij@linaro.org, arnd@arndb.de, niklas.hernaeus@stericsson.com, Lee Jones Subject: [PATCH 06/10] ARM: ux500: Enable Cortex-A9 GIC (Generic Interrupt Controller) in Device Tree Date: Wed, 14 Mar 2012 13:05:02 +0000 Message-Id: <1331730306-11461-7-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1331730306-11461-1-git-send-email-lee.jones@linaro.org> References: <1331730306-11461-1-git-send-email-lee.jones@linaro.org> X-Gm-Message-State: ALoCoQlOf+2HgSTwia/hOu1IRYPVG3bVDf2bcVKbtAGfafTLydp88ec5LcMxt89aiivni5DJ9w9F This enables the embedded GIC on all u8500 based hardware using DT. Signed-off-by: Lee Jones --- arch/arm/boot/dts/db8500.dtsi | 11 +++++++++++ arch/arm/mach-ux500/cpu.c | 12 +++++++++++- 2 files changed, 22 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index 0521cea..cce5df8 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -16,8 +16,19 @@ #address-cells = <1>; #size-cells = <1>; compatible = "stericsson,db8500"; + interrupt-parent = <&intc>; ranges; + intc: interrupt-controller@a0411000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + interrupt-parent; + reg = <0xa0411000 0x1000>, + <0xa0410100 0x100>; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <7>; diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 055fb6e..bd7f1dd 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include #include @@ -29,6 +31,11 @@ void __iomem *_PRCMU_BASE; +static const struct of_device_id ux500_dt_irq_match[] = { + { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, + {}, +}; + void __init ux500_init_irq(void) { void __iomem *dist_base; @@ -43,7 +50,10 @@ void __init ux500_init_irq(void) } else ux500_unknown_soc(); - gic_init(0, 29, dist_base, cpu_base); + if (of_have_populated_dt()) + of_irq_init(ux500_dt_irq_match); + else + gic_init(0, 29, dist_base, cpu_base); /* * Init clocks here so that they are available for system timer