From patchwork Wed Apr 18 22:41:47 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 7938 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 1073D23E12 for ; Wed, 18 Apr 2012 22:42:09 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id A1311A184B5 for ; Wed, 18 Apr 2012 22:42:08 +0000 (UTC) Received: by iage36 with SMTP id e36so15109345iag.11 for ; Wed, 18 Apr 2012 15:42:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:x-gm-message-state; bh=vcJ1mM+pJPxH85ETbKBEtp5uz4dvosKyDJRFk+OsASM=; b=ISaf2Wo5KkvjfujA7rOrsyWc/+BISscOSe3+/HYTXmjf4Ra7EMWp0j+kN48vrgCTsg 86j4qwAZd9Zx22LqzFGMOLKTEAG+FK6mJQT0ltbth65EmaVauogfMwR4pRt5agA7fv/B VF4g5NTxrf/kn4wMqUwtdVpjhAZkTy+v0bbIi5opmy8fGOcbqXq+6oiRNEVL8WWji4pE 6H6HpcZ0sY2KkbAUD2uWqupcrYy1MnaCilu3gb/MaxVxMD0DTTcGa4HURHkB/nx/PrXa A2JEq862m6KchHxaij2BHs/a2UW5Cu96Rgy2GmYKK42zmHCvVy5jHzelIOAcWzsuqcki t9Uw== Received: by 10.50.41.201 with SMTP id h9mr14926839igl.19.1334788927871; Wed, 18 Apr 2012 15:42:07 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.137.198 with SMTP id x6csp250136ibt; Wed, 18 Apr 2012 15:42:07 -0700 (PDT) Received: by 10.152.128.137 with SMTP id no9mr3804292lab.2.1334788925847; Wed, 18 Apr 2012 15:42:05 -0700 (PDT) Received: from mail.df.lth.se (mail.df.lth.se. [194.47.250.12]) by mx.google.com with ESMTPS id b9si96539lba.39.2012.04.18.15.42.04 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 18 Apr 2012 15:42:05 -0700 (PDT) Received-SPF: neutral (google.com: 194.47.250.12 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) client-ip=194.47.250.12; Authentication-Results: mx.google.com; spf=neutral (google.com: 194.47.250.12 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) smtp.mail=linus.walleij@linaro.org Received: from fecusia (c83-249-217-151.bredband.comhem.se [83.249.217.151]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.df.lth.se (Postfix) with ESMTPSA id C9B2F65D4E; Thu, 19 Apr 2012 00:42:02 +0200 (CEST) Received: by fecusia (sSMTP sendmail emulation); Thu, 19 Apr 2012 00:42:02 +0200 From: "Linus Walleij" To: linux-arm-kernel@lists.infradead.org Cc: Grant Likely , Rob Herring , Benjamin Herrenschmidt , Russell King - ARM Linux , Linus Walleij Subject: [PATCH] ARM: nomadik: bump all IRQ numbers by one Date: Thu, 19 Apr 2012 00:41:47 +0200 Message-Id: <1334788907-2113-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.7.7.6 X-Gm-Message-State: ALoCoQmDYbvJmlGcFe5OdYoTxsx9UDmHtv0dcke9AuJThophFtpjkt326Q6hMGbf85qvlICBDDwf Since the VIC was converted to use generic IRQ domains IRQ 0 is silently ignored. This IRQ is used on the Nomadik so we're missing it now. Bump all IRQ numbers by one since they are now decoupled from the hardware IRQ numbers. Cc: Grant Likely Cc: Rob Herring Signed-off-by: Linus Walleij --- arch/arm/mach-nomadik/include/mach/irqs.h | 79 ++++++++++++++--------------- 1 files changed, 39 insertions(+), 40 deletions(-) diff --git a/arch/arm/mach-nomadik/include/mach/irqs.h b/arch/arm/mach-nomadik/include/mach/irqs.h index 8faabc5..ffa0deb 100644 --- a/arch/arm/mach-nomadik/include/mach/irqs.h +++ b/arch/arm/mach-nomadik/include/mach/irqs.h @@ -22,49 +22,49 @@ #include -#define IRQ_VIC_START 0 /* first VIC interrupt is 0 */ +#define IRQ_VIC_START 1 /* first VIC interrupt is 1 */ /* * Interrupt numbers generic for all Nomadik Chip cuts */ -#define IRQ_WATCHDOG 0 -#define IRQ_SOFTINT 1 -#define IRQ_CRYPTO 2 -#define IRQ_OWM 3 -#define IRQ_MTU0 4 -#define IRQ_MTU1 5 -#define IRQ_GPIO0 6 -#define IRQ_GPIO1 7 -#define IRQ_GPIO2 8 -#define IRQ_GPIO3 9 -#define IRQ_RTC_RTT 10 -#define IRQ_SSP 11 -#define IRQ_UART0 12 -#define IRQ_DMA1 13 -#define IRQ_CLCD_MDIF 14 -#define IRQ_DMA0 15 -#define IRQ_PWRFAIL 16 -#define IRQ_UART1 17 -#define IRQ_FIRDA 18 -#define IRQ_MSP0 19 -#define IRQ_I2C0 20 -#define IRQ_I2C1 21 -#define IRQ_SDMMC 22 -#define IRQ_USBOTG 23 -#define IRQ_SVA_IT0 24 -#define IRQ_SVA_IT1 25 -#define IRQ_SAA_IT0 26 -#define IRQ_SAA_IT1 27 -#define IRQ_UART2 28 -#define IRQ_MSP2 31 -#define IRQ_L2CC 48 -#define IRQ_HPI 49 -#define IRQ_SKE 50 -#define IRQ_KP 51 -#define IRQ_MEMST 54 -#define IRQ_SGA_IT 58 -#define IRQ_USBM 60 -#define IRQ_MSP1 62 +#define IRQ_WATCHDOG 1 +#define IRQ_SOFTINT 2 +#define IRQ_CRYPTO 3 +#define IRQ_OWM 4 +#define IRQ_MTU0 5 +#define IRQ_MTU1 6 +#define IRQ_GPIO0 7 +#define IRQ_GPIO1 8 +#define IRQ_GPIO2 9 +#define IRQ_GPIO3 10 +#define IRQ_RTC_RTT 11 +#define IRQ_SSP 12 +#define IRQ_UART0 13 +#define IRQ_DMA1 14 +#define IRQ_CLCD_MDIF 15 +#define IRQ_DMA0 16 +#define IRQ_PWRFAIL 17 +#define IRQ_UART1 18 +#define IRQ_FIRDA 19 +#define IRQ_MSP0 20 +#define IRQ_I2C0 21 +#define IRQ_I2C1 22 +#define IRQ_SDMMC 23 +#define IRQ_USBOTG 24 +#define IRQ_SVA_IT0 25 +#define IRQ_SVA_IT1 26 +#define IRQ_SAA_IT0 27 +#define IRQ_SAA_IT1 28 +#define IRQ_UART2 29 +#define IRQ_MSP2 30 +#define IRQ_L2CC 49 +#define IRQ_HPI 50 +#define IRQ_SKE 51 +#define IRQ_KP 52 +#define IRQ_MEMST 55 +#define IRQ_SGA_IT 59 +#define IRQ_USBM 61 +#define IRQ_MSP1 63 #define NOMADIK_SOC_NR_IRQS 64 @@ -79,4 +79,3 @@ #define VIC_REG_IRQSR1 0x20 #endif /* __ASM_ARCH_IRQS_H */ -