From patchwork Fri Sep 14 21:34:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 11435 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 3C072240A0 for ; Fri, 14 Sep 2012 21:35:39 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id F0286A3926F for ; Fri, 14 Sep 2012 21:35:32 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id j25so3512531iaf.11 for ; Fri, 14 Sep 2012 14:35:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-provags-id:x-gm-message-state; bh=kp2Lvh29elLZN/tdIsk60ACP4YpYloa91wbmY/lnjQ4=; b=mHO3/IleN/H60FNajnZV8dPinxqtdL/T5Cv3+yvDSQH3wxu2Ff1AI1Aa5uAAfrfleH ZmuaZ3UjJBx86zo62MrWnpr3cMlscAZ88DchX2JLh7sTQcQiUFUH4sMuSJzM7MZSXqFg lwxABZmT4oBpSrxz8RvsCNPn2FFQ2QZptAyXODI6KBFxgit5UDL3eqWYjTH+NONJ0EQW a7EtLmxQ61NMVb+rYSwqv04eGlVQhS8pfWTy7oBKwYlCSH00JcUin6mLKDz09JSffdT7 sTGeCh7QsE8kXRcSFik2j18lkYGGYjzkVuEdRFZnYZYB5VmC+szhMMXQBlGtAFIzqakq 5IsA== Received: by 10.50.191.227 with SMTP id hb3mr107161igc.43.1347658532751; Fri, 14 Sep 2012 14:35:32 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp215414igc; Fri, 14 Sep 2012 14:35:31 -0700 (PDT) Received: by 10.204.130.209 with SMTP id u17mr2181219bks.35.1347658531232; Fri, 14 Sep 2012 14:35:31 -0700 (PDT) Received: from moutng.kundenserver.de (moutng.kundenserver.de. [212.227.126.186]) by mx.google.com with ESMTP id gg16si4069861bkc.126.2012.09.14.14.35.30; Fri, 14 Sep 2012 14:35:31 -0700 (PDT) Received-SPF: neutral (google.com: 212.227.126.186 is neither permitted nor denied by best guess record for domain of arnd@arndb.de) client-ip=212.227.126.186; Authentication-Results: mx.google.com; spf=neutral (google.com: 212.227.126.186 is neither permitted nor denied by best guess record for domain of arnd@arndb.de) smtp.mail=arnd@arndb.de Received: from localhost.localdomain (HSI-KBW-149-172-5-253.hsi13.kabel-badenwuerttemberg.de [149.172.5.253]) by mrelayeu.kundenserver.de (node=mrbap2) with ESMTP (Nemesis) id 0MgI6w-1SrHCe42lC-00NDNt; Fri, 14 Sep 2012 23:35:23 +0200 From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Will Deacon , Russell King , Nicolas Pitre , Arnd Bergmann , Imre Kaloz , Krzysztof Halasa , Lennert Buytenhek Subject: [PATCH 08/24] ARM: iop32x: use __iomem pointers for MMIO Date: Fri, 14 Sep 2012 23:34:36 +0200 Message-Id: <1347658492-11608-9-git-send-email-arnd@arndb.de> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1347658492-11608-1-git-send-email-arnd@arndb.de> References: <1347658492-11608-1-git-send-email-arnd@arndb.de> X-Provags-ID: V02:K0:55dRg2RUrIbKzJ+fLFqM1RABXRkd+5fiyEzpJnp8yPf si/gHYeNjDx5mR1udZAl9fz9Xg2PME3urVA0qz6+oxIcNivM+3 8QvuUAbNZabQ3OgGkf+fX+80fxdmJ9BSuKnrTqNl0o7VoP6d1a a0ULnp13U3vok66GHe6hvKHEMhvKgTcwlLuYsnA6ZpEFmtvf8P Km2en2VU32BdZ97iJmrvSz3YDkay4hTOgcHXq5lwr6fkIMiACA 5uEaN+oH0eEXRN1cZ28QekHUNRvnUQ6TgIeGMgJlMWOPwjsNSY WoIBRg+0QrEzFHQPM5mu7JoImhtP+Iw7dvN4YhcYkDYLeDRpx1 8nsyTn1nz/KbWPEnQ84yz/Sz34gI+06WQxUH6AnUh5q8a6A0Fj 4oeAD8iaHa1YA== X-Gm-Message-State: ALoCoQljE+E1EuYmZ7MbFgHVC38LOhaLsY5dGgB3EG3TW/I+7/reC05f9YPzzjB8XUX7Za99TUQi ARM is moving to stricter checks on readl/write functions, so we need to use the correct types everywhere. Cc: Imre Kaloz Cc: Krzysztof Halasa Cc: Lennert Buytenhek Signed-off-by: Arnd Bergmann --- arch/arm/mach-iop32x/glantank.c | 2 +- arch/arm/mach-ixp4xx/common.c | 6 +++--- arch/arm/mach-ixp4xx/include/mach/cpu.h | 5 +++-- arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index c15a100..02e20c3 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c @@ -183,7 +183,7 @@ static struct i2c_board_info __initdata glantank_i2c_devices[] = { static void glantank_power_off(void) { - __raw_writeb(0x01, 0xfe8d0004); + __raw_writeb(0x01, IOMEM(0xfe8d0004)); while (1) ; diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index a9f8094..8c9cd5d 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -53,17 +53,17 @@ static struct clock_event_device clockevent_ixp4xx; *************************************************************************/ static struct map_desc ixp4xx_io_desc[] __initdata = { { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */ - .virtual = IXP4XX_PERIPHERAL_BASE_VIRT, + .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS), .length = IXP4XX_PERIPHERAL_REGION_SIZE, .type = MT_DEVICE }, { /* Expansion Bus Config Registers */ - .virtual = IXP4XX_EXP_CFG_BASE_VIRT, + .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS), .length = IXP4XX_EXP_CFG_REGION_SIZE, .type = MT_DEVICE }, { /* PCI Registers */ - .virtual = IXP4XX_PCI_CFG_BASE_VIRT, + .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS), .length = IXP4XX_PCI_CFG_REGION_SIZE, .type = MT_DEVICE diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h index b2ef65d..e3d5a2e 100644 --- a/arch/arm/mach-ixp4xx/include/mach/cpu.h +++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h @@ -14,6 +14,7 @@ #ifndef __ASM_ARCH_CPU_H__ #define __ASM_ARCH_CPU_H__ +#include #include /* Processor id value in CP15 Register 0 */ @@ -37,7 +38,7 @@ static inline u32 ixp4xx_read_feature_bits(void) { - u32 val = ~*IXP4XX_EXP_CFG2; + u32 val = ~__raw_readl(IXP4XX_EXP_CFG2); if (cpu_is_ixp42x_rev_a0()) return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP | @@ -51,7 +52,7 @@ static inline u32 ixp4xx_read_feature_bits(void) static inline void ixp4xx_write_feature_bits(u32 value) { - *IXP4XX_EXP_CFG2 = ~value; + __raw_writel(~cpu_to_le32(value), IXP4XX_EXP_CFG2); } #endif /* _ASM_ARCH_CPU_H */ diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h index 97c530f..2272f5a 100644 --- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h +++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h @@ -92,7 +92,7 @@ /* * Expansion Bus Controller registers. */ -#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) +#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)