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Tue, 04 Jun 2013 08:05:59 -0700 (PDT) X-Received: by 10.68.71.129 with SMTP id v1mr29374459pbu.136.1370358359429; Tue, 04 Jun 2013 08:05:59 -0700 (PDT) Received: from localhost.localdomain ([27.115.121.40]) by mx.google.com with ESMTPSA id ig4sm35557031pbc.18.2013.06.04.08.05.54 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 04 Jun 2013 08:05:58 -0700 (PDT) From: Haojian Zhuang To: arnd@arndb.de, linux@arm.linux.org.uk, linus.walleij@linaro.org, olof@lixom.net, rob.herring@calxeda.com, linux-arm-kernel@lists.infradead.org, pawel.moll@arm.com, swarren@nvidia.com, john.stultz@linaro.org, tglx@linutronix.de, mturquette@linaro.org Cc: patches@linaro.org, Haojian Zhuang Subject: [PATCH v2 3/6] clk: divider: add CLK_DIVIDER_HIWORD_MASK flag Date: Tue, 4 Jun 2013 23:05:14 +0800 Message-Id: <1370358317-12768-4-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1370358317-12768-1-git-send-email-haojian.zhuang@linaro.org> References: <1370358317-12768-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQlUyriHKiuW/XFq/HHPQogvPX9Gwfa2PNaEgmTlNQyp6Z17UF0GCZUz0AvqFgwdmTAjikPe X-Original-Sender: haojian.zhuang@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::229 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In Hisilicon Hi3620 clock divider register, 16-bit HIWORD is mask field. Support the HIWORD mask to reuse clock divider driver. Signed-off-by: Haojian Zhuang --- drivers/clk/clk-divider.c | 6 ++++++ include/linux/clk-provider.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 6d96741..4c344b4 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -220,6 +220,12 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, val = readl(divider->reg); val &= ~(div_mask(divider) << divider->shift); val |= value << divider->shift; + if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { + if (divider->width + divider->shift > 16) + pr_warn("divider value exceeds LOWORD field\n"); + else + val |= div_mask(divider) << (divider->shift + 16); + } writel(val, divider->reg); if (divider->lock) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 6ba32bc..dbb9bd9 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -257,6 +257,7 @@ struct clk_div_table { * Some hardware implementations gracefully handle this case and allow a * zero divisor by not modifying their input clock * (divide by one / bypass). + * CLK_DIVIDER_HIWORD_MASK - register contains high 16-bit as mask field */ struct clk_divider { struct clk_hw hw; @@ -271,6 +272,7 @@ struct clk_divider { #define CLK_DIVIDER_ONE_BASED BIT(0) #define CLK_DIVIDER_POWER_OF_TWO BIT(1) #define CLK_DIVIDER_ALLOW_ZERO BIT(2) +#define CLK_DIVIDER_HIWORD_MASK BIT(3) extern const struct clk_ops clk_divider_ops; struct clk *clk_register_divider(struct device *dev, const char *name,