From patchwork Thu Sep 26 19:01:33 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 20640 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qe0-f71.google.com (mail-qe0-f71.google.com [209.85.128.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 64BA923A4E for ; Thu, 26 Sep 2013 19:02:13 +0000 (UTC) Received: by mail-qe0-f71.google.com with SMTP id a11sf1440842qen.6 for ; Thu, 26 Sep 2013 12:02:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=Rf3L8zQPDSnWDjuGqaUZoYEPyWfQ7PGHjTWIQzBRsxA=; b=P9BrH8S6NNmZDuuyJwmq86aIzlJthSpLuKBw+qAmOJ6A5aVv/glM44rOOebPWVsDmT S6Gci0z9bsKhX+u9UHkoYAdCULfaeGnAiFJ8FRqVVko0/br/yUqwkSxMuBccAnyOcH6+ DWIZ20D63NuCzbqogLk0EE693LYJom76O2akGfA7cwQEox2Y2dfWeNjOMEq6rUl+PHFs OyHmA32z/3zJQf4MdxMedOXVNlTC5buhZvPKgtAcCWKXWNmazz0B7pCIcCCqz4SlnScw J7KDLbOw18ZO/epY0OH6fIcjzn2ipp67VO9CKab/u9+1N9CW7396LddC8CwPzj1VR1pP S4eQ== X-Gm-Message-State: ALoCoQkbRtrxMRmGzRhf4XFaZ22ErVAf3RtzZIws/hJ9Emmb2bQVCRbzj9Vq2InLaNypGMAcMsFX X-Received: by 10.236.220.39 with SMTP id n37mr505421yhp.15.1380222132995; Thu, 26 Sep 2013 12:02:12 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.108.230 with SMTP id hn6ls1055713qeb.81.gmail; Thu, 26 Sep 2013 12:02:12 -0700 (PDT) X-Received: by 10.58.28.147 with SMTP id b19mr1944862veh.27.1380222132912; Thu, 26 Sep 2013 12:02:12 -0700 (PDT) Received: from mail-vc0-f170.google.com (mail-vc0-f170.google.com [209.85.220.170]) by mx.google.com with ESMTPS id st7si767207vdc.68.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 26 Sep 2013 12:02:12 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.170; Received: by mail-vc0-f170.google.com with SMTP id lc6so868154vcb.1 for ; Thu, 26 Sep 2013 12:01:42 -0700 (PDT) X-Received: by 10.58.108.74 with SMTP id hi10mr2071000veb.14.1380222102780; Thu, 26 Sep 2013 12:01:42 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp383690vcz; Thu, 26 Sep 2013 12:01:42 -0700 (PDT) X-Received: by 10.68.134.133 with SMTP id pk5mr2840027pbb.89.1380222101920; Thu, 26 Sep 2013 12:01:41 -0700 (PDT) Received: from mail-pb0-f49.google.com (mail-pb0-f49.google.com [209.85.160.49]) by mx.google.com with ESMTPS id q7si477118pbd.64.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 26 Sep 2013 12:01:41 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.160.49 is neither permitted nor denied by best guess record for domain of christoffer.dall@linaro.org) client-ip=209.85.160.49; Received: by mail-pb0-f49.google.com with SMTP id xb4so1532504pbc.22 for ; Thu, 26 Sep 2013 12:01:41 -0700 (PDT) X-Received: by 10.66.65.108 with SMTP id w12mr5082497pas.183.1380222101490; Thu, 26 Sep 2013 12:01:41 -0700 (PDT) Received: from localhost.localdomain (c-67-169-181-221.hsd1.ca.comcast.net. [67.169.181.221]) by mx.google.com with ESMTPSA id k4sm3870767pbd.11.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 26 Sep 2013 12:01:40 -0700 (PDT) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linaro-kernel@lists.linaro.org, patches@linaro.org, Christoffer Dall , Thomas Gleixner Subject: [PATCH v2 4/8] irqchip: arm-gic: Define additional MMIO offsets and masks Date: Thu, 26 Sep 2013 12:01:33 -0700 Message-Id: <1380222097-20251-5-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1380222097-20251-1-git-send-email-christoffer.dall@linaro.org> References: <1380222097-20251-1-git-send-email-christoffer.dall@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: christoffer.dall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Define CPU interface offsets for the GICC_ABPR, GICC_APR, and GICC_IIDR registers. Define distributor registers for the GICD_SPENDSGIR and the GICD_CPENDSGIR. KVM/ARM needs to know about these definitions to fully support save/restore of the VGIC. Also define some masks and shifts for the various GICH_VMCR fields. Cc: Thomas Gleixner Signed-off-by: Christoffer Dall Reviewed-by: Alexander Graf --- include/linux/irqchip/arm-gic.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index 0e5d9ec..28b28fc 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h @@ -17,6 +17,9 @@ #define GIC_CPU_EOI 0x10 #define GIC_CPU_RUNNINGPRI 0x14 #define GIC_CPU_HIGHPRI 0x18 +#define GIC_CPU_ALIAS_BINPOINT 0x1c +#define GIC_CPU_ACTIVEPRIO 0xd0 +#define GIC_CPU_IDENT 0xfc #define GIC_DIST_CTRL 0x000 #define GIC_DIST_CTR 0x004 @@ -31,6 +34,8 @@ #define GIC_DIST_TARGET 0x800 #define GIC_DIST_CONFIG 0xc00 #define GIC_DIST_SOFTINT 0xf00 +#define GIC_DIST_SGI_CLEAR 0xf10 +#define GIC_DIST_SGI_SET 0xf20 #define GICH_HCR 0x0 #define GICH_VTR 0x4 @@ -54,6 +59,15 @@ #define GICH_LR_ACTIVE_BIT (1 << 29) #define GICH_LR_EOI (1 << 19) +#define GICH_VMCR_CTRL_SHIFT 0 +#define GICH_VMCR_CTRL_MASK (0x21f << GICH_VMCR_CTRL_SHIFT) +#define GICH_VMCR_PRIMASK_SHIFT 27 +#define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT) +#define GICH_VMCR_BINPOINT_SHIFT 21 +#define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT) +#define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18 +#define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT) + #define GICH_MISR_EOI (1 << 0) #define GICH_MISR_U (1 << 1)