From patchwork Tue Nov 12 13:48:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 21459 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-vc0-f197.google.com (mail-vc0-f197.google.com [209.85.220.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id C636523FBE for ; Tue, 12 Nov 2013 13:48:26 +0000 (UTC) Received: by mail-vc0-f197.google.com with SMTP id if17sf4681vcb.8 for ; Tue, 12 Nov 2013 05:48:26 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=cHIkIllYLlV7owLzK6nk0wXuIp3dARBZ+8Zl3B06Z/I=; b=ReyP4vqKcKG3dTn1sIIsioVpbCfbqypuGR2mcpUUuLXQAU8D+kSzoNTlvUusoRiNsy eObNKVR0D0kjQjxmOD/PUOx7wPwyttW6/4igyQ6sTu7chiZqdoY05LdHc6QBvETc9oFJ Q5rrZUZ2K1D+4wWAydPzwellWB0alMWv2jHwlBhMf0hVzUWFXhFXJh2j9FPBT6gXQbJB NSetSdG4e8W33SHl0atChBw/SQOKfb3m4fuSBcNtQQ8fjZQJb1C1PZDUngWtQmxLiWgw xxkUIhfC3FLLFDsPT+ZVE4Zz75pHsbcz6pcQN4NR5x5jd3z+6k4FRpAKU1ldqpeccNyx 737A== X-Gm-Message-State: ALoCoQkKauDp69x20QtVJr69u9VcanuWaVIU/Kn6rYIcS/J8Y0ayXzB1usFZa6FvJOurIAFcBbAi X-Received: by 10.236.136.199 with SMTP id w47mr67500yhi.56.1384264106622; Tue, 12 Nov 2013 05:48:26 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.82.229 with SMTP id l5ls104601qey.11.gmail; Tue, 12 Nov 2013 05:48:26 -0800 (PST) X-Received: by 10.52.171.79 with SMTP id as15mr25128082vdc.1.1384264106533; Tue, 12 Nov 2013 05:48:26 -0800 (PST) Received: from mail-vb0-f53.google.com (mail-vb0-f53.google.com [209.85.212.53]) by mx.google.com with ESMTPS id hr2si12031217vdb.89.2013.11.12.05.48.26 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 12 Nov 2013 05:48:26 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.53 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.53; Received: by mail-vb0-f53.google.com with SMTP id x17so653057vbf.40 for ; Tue, 12 Nov 2013 05:48:26 -0800 (PST) X-Received: by 10.58.232.228 with SMTP id tr4mr429615vec.34.1384264106443; Tue, 12 Nov 2013 05:48:26 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp163921vcz; Tue, 12 Nov 2013 05:48:25 -0800 (PST) X-Received: by 10.180.100.194 with SMTP id fa2mr16556551wib.44.1384264105474; Tue, 12 Nov 2013 05:48:25 -0800 (PST) Received: from mail-wi0-f182.google.com (mail-wi0-f182.google.com [209.85.212.182]) by mx.google.com with ESMTPS id hj12si7780610wib.69.2013.11.12.05.48.25 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 12 Nov 2013 05:48:25 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.182 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) client-ip=209.85.212.182; Received: by mail-wi0-f182.google.com with SMTP id ez12so3723308wid.15 for ; Tue, 12 Nov 2013 05:48:25 -0800 (PST) X-Received: by 10.180.221.67 with SMTP id qc3mr16533207wic.14.1384264105050; Tue, 12 Nov 2013 05:48:25 -0800 (PST) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id ft19sm44718724wic.5.2013.11.12.05.48.23 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Nov 2013 05:48:24 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Russell King Cc: Andrea Adami , Dmitry Eremin-Solenikov , Dmitry Artamonow , Dmitry Eremin-Solenikov , Linus Walleij Subject: [PATCH 4/7] ARM: sa1100: use hardware IRQ bit masks Date: Tue, 12 Nov 2013 14:48:21 +0100 Message-Id: <1384264101-6326-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.3.1 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.53 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , By using the hardware IRQ number, and setting that to offset from 11 for the high GPIOs, we can get this number to match the bit in the GPIO edge control registers for both low and high GPIOs and we can simplify the code a bit. Signed-off-by: Linus Walleij --- arch/arm/mach-sa1100/irq.c | 34 +++++++++++----------------------- 1 file changed, 11 insertions(+), 23 deletions(-) diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index bf36b9abfaad..4b1e6bb60e5e 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c @@ -36,20 +36,9 @@ static int GPIO_IRQ_rising_edge; static int GPIO_IRQ_falling_edge; static int GPIO_IRQ_mask = (1 << 11) - 1; -/* - * To get the GPIO number from an IRQ number - */ -#define GPIO_11_27_IRQ(i) ((i) - 21) -#define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq)) - static int sa1100_gpio_type(struct irq_data *d, unsigned int type) { - unsigned int mask; - - if (d->irq <= 10) - mask = 1 << d->irq; - else - mask = GPIO11_27_MASK(d->irq); + unsigned int mask = BIT(d->hwirq); if (type == IRQ_TYPE_PROBE) { if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) @@ -131,20 +120,19 @@ sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc) } /* - * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially. - * In addition, the IRQs are all collected up into one bit in the - * interrupt controller registers. + * GPIO 11 thru GPIO 27 IRQs need to be handled specially. + * These all trigger IRQ 11 on the interrupt controller, so we + * need to use the GPIO edge detect status register to see + * which GPIO was firing the IRQ. */ static void sa1100_high_gpio_ack(struct irq_data *d) { - unsigned int mask = GPIO11_27_MASK(d->irq); - - GEDR = mask; + GEDR = BIT(d->hwirq); } static void sa1100_high_gpio_mask(struct irq_data *d) { - unsigned int mask = GPIO11_27_MASK(d->irq); + unsigned int mask = BIT(d->hwirq); GPIO_IRQ_mask &= ~mask; @@ -154,7 +142,7 @@ static void sa1100_high_gpio_mask(struct irq_data *d) static void sa1100_high_gpio_unmask(struct irq_data *d) { - unsigned int mask = GPIO11_27_MASK(d->irq); + unsigned int mask = BIT(d->hwirq); GPIO_IRQ_mask |= mask; @@ -165,9 +153,9 @@ static void sa1100_high_gpio_unmask(struct irq_data *d) static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on) { if (on) - PWER |= GPIO11_27_MASK(d->irq); + PWER |= BIT(d->hwirq); else - PWER &= ~GPIO11_27_MASK(d->irq); + PWER &= ~BIT(d->hwirq); return 0; } @@ -392,7 +380,7 @@ void __init sa1100_init_irq(void) /* Register IRQs 0-31 using a legacy irqdomain */ sc->domain = irq_domain_add_legacy(NULL, 32, 0, 0, &sa1100_sc_irqdomain_ops, sc); - sc->high_domain = irq_domain_add_legacy(NULL, 17, 32, 0, + sc->high_domain = irq_domain_add_legacy(NULL, 17, 32, 11, &sa1100_sc_high_irqdomain_ops, sc); sa1100_init_gpio(); }