From patchwork Tue Nov 12 13:48:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 21460 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qe0-f70.google.com (mail-qe0-f70.google.com [209.85.128.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 817A623FBE for ; Tue, 12 Nov 2013 13:48:35 +0000 (UTC) Received: by mail-qe0-f70.google.com with SMTP id 8sf10119666qea.9 for ; Tue, 12 Nov 2013 05:48:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=SJGDBqB0gAyk0+zEUaUR526WIbsFA8nN5BVAwRYs1sw=; b=EHxnFTm14907YmZCKjJMe7d48GR+RyzOaQ+PwGuShXI7lnUaSyHgOZLSeyOHRYOXGf uO5kg3QtyfbUhxmlv5YO5q3h5/985gKZpO04lJeLEIM3HbGNb2B6cbYfi14Br6z8rqkX SoMykor2+e76h2K7BSH8q3ym2jpTOC42wayej+WhHb/Kp/IytcHFDxVDJcUOXb2mq0nl EP88fdavGpNTVPjvFnXAuMi7wxI6BkwyxuMPEbgHF05SGGxRMMbAudyhB5MekdR1ldem lX0ykKX3vCMZiQQmbda8Pp74fa1pbVze0hLKniJCpaHODW7kCyrFr69HuM54KfjbP4Rh bhOg== X-Gm-Message-State: ALoCoQlUN8iAOUKhGzy98dcodMZ6Rd7rqp+G5k/vCysdh1gRHAJhXlXOPl1DfXcrJ5ivXcQjyC1d X-Received: by 10.224.111.201 with SMTP id t9mr11137416qap.8.1384264115097; Tue, 12 Nov 2013 05:48:35 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.83.198 with SMTP id s6ls105543qey.46.gmail; Tue, 12 Nov 2013 05:48:35 -0800 (PST) X-Received: by 10.58.54.69 with SMTP id h5mr2956245vep.25.1384264115008; Tue, 12 Nov 2013 05:48:35 -0800 (PST) Received: from mail-vb0-f42.google.com (mail-vb0-f42.google.com [209.85.212.42]) by mx.google.com with ESMTPS id a6si12025500vdp.104.2013.11.12.05.48.34 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 12 Nov 2013 05:48:34 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.42 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.42; Received: by mail-vb0-f42.google.com with SMTP id p14so4352691vbm.29 for ; Tue, 12 Nov 2013 05:48:34 -0800 (PST) X-Received: by 10.58.67.168 with SMTP id o8mr9356223vet.22.1384264114910; Tue, 12 Nov 2013 05:48:34 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp163926vcz; Tue, 12 Nov 2013 05:48:34 -0800 (PST) X-Received: by 10.205.36.202 with SMTP id tb10mr125051bkb.119.1384264113842; Tue, 12 Nov 2013 05:48:33 -0800 (PST) Received: from mail-bk0-f50.google.com (mail-bk0-f50.google.com [209.85.214.50]) by mx.google.com with ESMTPS id yz9si4447641bkb.281.2013.11.12.05.48.33 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 12 Nov 2013 05:48:33 -0800 (PST) Received-SPF: neutral (google.com: 209.85.214.50 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) client-ip=209.85.214.50; Received: by mail-bk0-f50.google.com with SMTP id v16so247700bkz.23 for ; Tue, 12 Nov 2013 05:48:33 -0800 (PST) X-Received: by 10.205.24.131 with SMTP id re3mr25821857bkb.8.1384264113200; Tue, 12 Nov 2013 05:48:33 -0800 (PST) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id pn6sm18256711bkb.14.2013.11.12.05.48.31 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Nov 2013 05:48:32 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Russell King Cc: Andrea Adami , Dmitry Eremin-Solenikov , Dmitry Artamonow , Dmitry Eremin-Solenikov , Linus Walleij Subject: [PATCH 5/7] ARM: sa1100: move GPIO masks to state container Date: Tue, 12 Nov 2013 14:48:29 +0100 Message-Id: <1384264109-6361-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.3.1 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.42 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Move the masks for the GPIO edges into the SC state container so that we can get rid of the file-local variables. Define the default-on mask for GPIOs 0 thru 11 by a hex value instead of BIT(11) - 1 as the inverse of this hex value is used in the sa1100_high_gpio_handler() function. Signed-off-by: Linus Walleij --- arch/arm/mach-sa1100/irq.c | 98 +++++++++++++++++++++++++--------------------- 1 file changed, 54 insertions(+), 44 deletions(-) diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index 4b1e6bb60e5e..5463ba521ac7 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c @@ -27,36 +27,53 @@ #include "generic.h" -/* - * SA1100 GPIO edge detection for IRQs: - * IRQs are generated on Falling-Edge, Rising-Edge, or both. - * Use this instead of directly setting GRER/GFER. +/** + * struct sa1100_sc - SA1100 interrupt controller + * @domain: irqdomain used to map the irqs for these chips + * @low_gpio_chip: irqchip to handle hardware IRQs 0-10 + * @normal_chip: irqchip to handle hardware IRQs 12-31 + * @high_domain: irqdomain for the high GPIO IRQs + * @high_gpio_chip: irqchip handling the cascaded IRQs off + * IRQ 11 on the normal chip. + * @gpio_rising: whether the IRQ for the GPIO corresponding to the + * bit in this word should trigger on rising edges. + * @gpio_falling: whether the IRQ for the GPIO corresponding to the + * bit in this word should trigger on falling edges. + * @gpio_mask: whether this GPIO is masked off. */ -static int GPIO_IRQ_rising_edge; -static int GPIO_IRQ_falling_edge; -static int GPIO_IRQ_mask = (1 << 11) - 1; +struct sa1100_sc { + struct irq_domain *domain; + struct irq_chip low_gpio_chip; + struct irq_chip normal_chip; + struct irq_domain *high_domain; + struct irq_chip high_gpio_chip; + u32 gpio_rising; + u32 gpio_falling; + u32 gpio_mask; +}; static int sa1100_gpio_type(struct irq_data *d, unsigned int type) { + struct sa1100_sc *sc = irq_data_get_irq_chip_data(d); unsigned int mask = BIT(d->hwirq); if (type == IRQ_TYPE_PROBE) { - if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) + if ((sc->gpio_rising | sc->gpio_falling) & mask) return 0; type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; } - if (type & IRQ_TYPE_EDGE_RISING) { - GPIO_IRQ_rising_edge |= mask; - } else - GPIO_IRQ_rising_edge &= ~mask; - if (type & IRQ_TYPE_EDGE_FALLING) { - GPIO_IRQ_falling_edge |= mask; - } else - GPIO_IRQ_falling_edge &= ~mask; + if (type & IRQ_TYPE_EDGE_RISING) + sc->gpio_rising |= mask; + else + sc->gpio_rising &= ~mask; + if (type & IRQ_TYPE_EDGE_FALLING) + sc->gpio_falling |= mask; + else + sc->gpio_falling &= ~mask; - GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; - GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; + GRER = sc->gpio_rising & sc->gpio_mask; + GFER = sc->gpio_falling & sc->gpio_mask; return 0; } @@ -132,22 +149,23 @@ static void sa1100_high_gpio_ack(struct irq_data *d) static void sa1100_high_gpio_mask(struct irq_data *d) { + struct sa1100_sc *sc = irq_data_get_irq_chip_data(d); unsigned int mask = BIT(d->hwirq); - GPIO_IRQ_mask &= ~mask; - + sc->gpio_mask &= ~mask; GRER &= ~mask; GFER &= ~mask; } static void sa1100_high_gpio_unmask(struct irq_data *d) { + struct sa1100_sc *sc = irq_data_get_irq_chip_data(d); unsigned int mask = BIT(d->hwirq); - GPIO_IRQ_mask |= mask; + sc->gpio_mask |= mask; - GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; - GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; + GRER = sc->gpio_rising & sc->gpio_mask; + GFER = sc->gpio_falling & sc->gpio_mask; } static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on) @@ -188,23 +206,6 @@ static int sa1100_set_wake(struct irq_data *d, unsigned int on) return -EINVAL; } -/** - * struct sa1100_sc - SA1100 interrupt controller - * @domain: irqdomain used to map the irqs for these chips - * @low_gpio_chip: irqchip to handle hardware IRQs 0-10 - * @normal_chip: irqchip to handle hardware IRQs 12-31 - * @high_domain: irqdomain for the high GPIO IRQs - * @high_gpio_chip: irqchip handling the cascaded IRQs off - * IRQ 11 on the normal chip. - */ -struct sa1100_sc { - struct irq_domain *domain; - struct irq_chip low_gpio_chip; - struct irq_chip normal_chip; - struct irq_domain *high_domain; - struct irq_chip high_gpio_chip; -}; - static struct sa1100_sc sa1100_sc = { .low_gpio_chip = { .name = "GPIO-l", @@ -229,6 +230,13 @@ static struct sa1100_sc sa1100_sc = { .irq_set_type = sa1100_gpio_type, .irq_set_wake = sa1100_high_gpio_wake, }, + /* + * This will enable IRQ on GPIOs 0 thru 11 by default, so + * that they always fall through to the normal IRQ controller + * where they can be masked on/off using that IRQ controllers + * mask operations. + */ + .gpio_mask = 0x000007ff, }; asmlinkage void __exception_irq_entry sa1100_handle_irq(struct pt_regs *regs) @@ -298,6 +306,7 @@ static struct sa1100irq_state { static int sa1100irq_suspend(void) { + struct sa1100_sc *sc = &sa1100_sc; struct sa1100irq_state *st = &sa1100irq_state; st->saved = 1; @@ -315,8 +324,8 @@ static int sa1100irq_suspend(void) /* * Set the appropriate edges for wakeup. */ - GRER = PWER & GPIO_IRQ_rising_edge; - GFER = PWER & GPIO_IRQ_falling_edge; + GRER = PWER & sc->gpio_rising; + GFER = PWER & sc->gpio_falling; /* * Clear any pending GPIO interrupts. @@ -328,14 +337,15 @@ static int sa1100irq_suspend(void) static void sa1100irq_resume(void) { + struct sa1100_sc *sc = &sa1100_sc; struct sa1100irq_state *st = &sa1100irq_state; if (st->saved) { ICCR = st->iccr; ICLR = st->iclr; - GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask; - GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask; + GRER = sc->gpio_rising & sc->gpio_mask; + GFER = sc->gpio_falling & sc->gpio_mask; ICMR = st->icmr; }