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[2001:770:15f::2]) by mx.google.com with ESMTPS id ua15si1167618wib.15.2014.03.21.06.56.06 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Mar 2014 06:56:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:770:15f::2 as permitted sender) client-ip=2001:770:15f::2; Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WQzvQ-0005p3-GQ; Fri, 21 Mar 2014 13:55:56 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WQzvO-0006eR-3T; Fri, 21 Mar 2014 13:55:54 +0000 Received: from mail-wi0-f172.google.com ([209.85.212.172]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WQzvL-0006dY-PO for linux-arm-kernel@lists.infradead.org; Fri, 21 Mar 2014 13:55:52 +0000 Received: by mail-wi0-f172.google.com with SMTP id hi5so518542wib.17 for ; Fri, 21 Mar 2014 06:55:29 -0700 (PDT) X-Received: by 10.194.92.228 with SMTP id cp4mr1708458wjb.81.1395410127165; Fri, 21 Mar 2014 06:55:27 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id fo6sm5018567wib.7.2014.03.21.06.55.25 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Mar 2014 06:55:26 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Russell King Subject: [PATCH] ARM: ux500: remove pointless cache setup args Date: Fri, 21 Mar 2014 14:55:13 +0100 Message-Id: <1395410113-19965-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.5.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140321_095552_036523_E1FD6055 X-CRM114-Status: GOOD ( 14.30 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.172 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Linus Walleij X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This removes the setup of the l2x0 lines that are essentially just noops bouncing on the hardware as the cache registers are protected in the secure world and there is no point in writing them. Put in (0, ~0) to the l2x0_of_init() function as suggested by Russell and cut the complex code out. Reported-by: Russell King Signed-off-by: Linus Walleij --- Russell: I don't know how this fits with other changes hitting the l2x0 code, this file is pretty much stand-alone and orthogonal to any other stuff hitting the Ux500 code, so I can put it in your patch tracker if you want to take it or some version of it into your tree. --- arch/arm/mach-ux500/cache-l2x0.c | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index 264f894c0e3d..b535fc8f38bf 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -7,17 +7,15 @@ #include #include -#include #include #include "db8500-regs.h" #include "id.h" -static void __iomem *l2x0_base; - static int __init ux500_l2x0_unlock(void) { int i; + void __iomem *l2x0_base = __io_address(U8500_L2CC_BASE); /* * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions @@ -37,30 +35,13 @@ static int __init ux500_l2x0_unlock(void) static int __init ux500_l2x0_init(void) { - u32 aux_val = 0x3e000000; - - if (cpu_is_u8500_family() || cpu_is_ux540_family()) - l2x0_base = __io_address(U8500_L2CC_BASE); - else - /* Non-Ux500 platform */ + /* Needed for multiplatform boots */ + if (!(cpu_is_u8500_family() || cpu_is_ux540_family())) return -ENODEV; /* Unlock before init */ ux500_l2x0_unlock(); - - /* DBx540's L2 has 128KB way size */ - if (cpu_is_ux540_family()) - /* 128KB way size */ - aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); - else - /* 64KB way size */ - aux_val |= (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); - - /* 64KB way size, 8 way associativity, force WA */ - if (of_have_populated_dt()) - l2x0_of_init(aux_val, 0xc0000fff); - else - l2x0_init(l2x0_base, aux_val, 0xc0000fff); + l2x0_of_init(0, ~0); /* * We can't disable l2 as we are in non secure mode, currently