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[71.195.31.37]) by mx.google.com with ESMTPSA id t1sm6385811igw.16.2014.04.08.15.30.52 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 08 Apr 2014 15:30:52 -0700 (PDT) From: Alex Elder To: viresh.linux@gmail.com, shiraz.hashim@gmail.com Cc: spear-devel@list.st.com, vk.vipin@gmail.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH RESEND] ARM: spear: send SGI to trigger secondary CPU start Date: Tue, 8 Apr 2014 17:31:28 -0500 Message-Id: <1396996288-32020-1-git-send-email-elder@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: elder@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The ARM spear machine uses the "holding pen" mechanism for starting secondary CPUs. Most implementations indicate it's a secondary core's time to start by writing its CPU id into a location and then signaling the core with a software-generated interrupt. The spear code does not send the signal. Comments elsewhere in the code seem to indicate it should: The BootMonitor waits until it receives a soft interrupt, and then the secondary CPU branches to this address. I suspect this is an oversight, and this patch proposes a remedy. *** I need the attention of a maintainer to verify this *** because I am unable to test this proposed change. Signed-off-by: Alex Elder --- arch/arm/mach-spear/platsmp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c index 5c4a198..c9064fe 100644 --- a/arch/arm/mach-spear/platsmp.c +++ b/arch/arm/mach-spear/platsmp.c @@ -62,6 +62,8 @@ static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle) flush_cache_all(); outer_flush_all(); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { smp_rmb();