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[209.132.180.67]) by mx.google.com with ESMTP id qe5si1341172pbc.453.2014.05.14.11.18.00; Wed, 14 May 2014 11:18:00 -0700 (PDT) Received-SPF: none (google.com: linux-crypto-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751173AbaENSSA (ORCPT ); Wed, 14 May 2014 14:18:00 -0400 Received: from mail-yk0-f176.google.com ([209.85.160.176]:38919 "EHLO mail-yk0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751143AbaENSR7 (ORCPT ); Wed, 14 May 2014 14:17:59 -0400 Received: by mail-yk0-f176.google.com with SMTP id q9so1896509ykb.35 for ; Wed, 14 May 2014 11:17:59 -0700 (PDT) X-Received: by 10.236.178.39 with SMTP id e27mr868167yhm.98.1400091479123; Wed, 14 May 2014 11:17:59 -0700 (PDT) Received: from ards-macbook-pro.swisscom.com ([12.153.182.133]) by mx.google.com with ESMTPSA id c66sm3641080yhk.23.2014.05.14.11.17.56 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 14 May 2014 11:17:58 -0700 (PDT) From: Ard Biesheuvel To: catalin.marinas@arm.com, jussi.kivilinna@iki.fi, herbert@gondor.apana.org.au Cc: linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org, Ard Biesheuvel Subject: [PATCH v2 08/11] arm64/crypto: add shared macro to test for NEED_RESCHED Date: Wed, 14 May 2014 11:17:28 -0700 Message-Id: <1400091451-9117-9-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1400091451-9117-1-git-send-email-ard.biesheuvel@linaro.org> References: <1400091451-9117-1-git-send-email-ard.biesheuvel@linaro.org> Sender: linux-crypto-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-crypto@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This adds the asm macro definition 'b_if_no_resched' that performs a conditional branch depending on the preempt need_resched state. Signed-off-by: Ard Biesheuvel --- arch/arm64/include/asm/assembler.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index fd3e3924041b..296105fd3021 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -22,6 +22,11 @@ #include +#if defined(CONFIG_PREEMPT) || defined(CONFIG_PREEMPT_VOLUNTARY) +#include +#include +#endif + /* * Stack pushing/popping (register pairs only). Equivalent to store decrement * before, load increment after. @@ -146,3 +151,19 @@ lr .req x30 // link register #endif orr \rd, \lbits, \hbits, lsl #32 .endm + +/* + * Branch to 'lb' but only if we have not been tagged for preemption. + * + * Expects current->thread_info in ti, or NULL if running in interrupt + * context. reg is a scratch x register. + */ + .macro b_if_no_resched, ti, reg, lb +#if defined(CONFIG_PREEMPT) || defined(CONFIG_PREEMPT_VOLUNTARY) + cbz \ti, \lb /* have thread_info? */ + ldr \reg, [\ti, #TI_FLAGS] /* get flags */ + tbz \reg, #TIF_NEED_RESCHED, \lb /* need rescheduling? */ +#else + b \lb +#endif + .endm