From patchwork Fri Jun 27 18:04:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 32634 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pa0-f71.google.com (mail-pa0-f71.google.com [209.85.220.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 95F27201EF for ; Fri, 27 Jun 2014 18:04:45 +0000 (UTC) Received: by mail-pa0-f71.google.com with SMTP id eu11sf21567316pac.6 for ; Fri, 27 Jun 2014 11:04:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=lpjkHJR7jVd1CLE0DXLeoGnKp6QHryz5f/FXaAbOJPI=; b=kyWzg8D+9xrcBJvYLg0l6fcTpowQhef2G53KvXa6CJiTKlKcJ0I9cYi5t6AKA02vgY Sf3tf9oAz2JiDDZAu5acyH/NnB6a7iJ00ak3LEZbZy0+4+nHyiOSza01BU62kNzjXXf7 bwJ3ww+HADN+80vgMfPTQhnPkR32l8JQfEVL9v7GCo56IeNKyCQnxnYznGkQpm4Y3VNQ fO7y5tLsYIFD2J0dQq5ZwMH+tkD5Sd/xkUSzdK6HEbn4VdcPCCBOhXsWriCerDy5TXBq j5RyiiWsozPi2Qi3ZY06vUhUNKPJ8XwI/mvqJvERlMGDjol9pyJMcWNrs0P2JrGrDMby 6CVA== X-Gm-Message-State: ALoCoQm7mGnWu2HOSNMvP6OLjmxAwPiCD0lWB1uFlnc0Xeouav9pn09IZTFPJLkMcMjWjSk/4y+W X-Received: by 10.66.169.79 with SMTP id ac15mr13011820pac.48.1403892284750; Fri, 27 Jun 2014 11:04:44 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.109.33 with SMTP id k30ls684701qgf.15.gmail; Fri, 27 Jun 2014 11:04:44 -0700 (PDT) X-Received: by 10.53.7.204 with SMTP id de12mr15570919vdd.41.1403892284620; Fri, 27 Jun 2014 11:04:44 -0700 (PDT) Received: from mail-vc0-f181.google.com (mail-vc0-f181.google.com [209.85.220.181]) by mx.google.com with ESMTPS id dj5si6777420vcb.21.2014.06.27.11.04.44 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 27 Jun 2014 11:04:44 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.181 as permitted sender) client-ip=209.85.220.181; Received: by mail-vc0-f181.google.com with SMTP id il7so5399609vcb.40 for ; Fri, 27 Jun 2014 11:04:44 -0700 (PDT) X-Received: by 10.58.151.211 with SMTP id us19mr8925021veb.5.1403892284498; Fri, 27 Jun 2014 11:04:44 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp126761vcb; Fri, 27 Jun 2014 11:04:44 -0700 (PDT) X-Received: by 10.68.106.194 with SMTP id gw2mr32946142pbb.85.1403892283693; Fri, 27 Jun 2014 11:04:43 -0700 (PDT) Received: from mail-pa0-f46.google.com (mail-pa0-f46.google.com [209.85.220.46]) by mx.google.com with ESMTPS id rc6si14748011pab.107.2014.06.27.11.04.43 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 27 Jun 2014 11:04:43 -0700 (PDT) Received-SPF: pass (google.com: domain of mathieu.poirier@linaro.org designates 209.85.220.46 as permitted sender) client-ip=209.85.220.46; Received: by mail-pa0-f46.google.com with SMTP id eu11so4891087pac.33 for ; Fri, 27 Jun 2014 11:04:43 -0700 (PDT) X-Received: by 10.66.120.201 with SMTP id le9mr31888366pab.98.1403892283315; Fri, 27 Jun 2014 11:04:43 -0700 (PDT) Received: from t430.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [70.73.24.112]) by mx.google.com with ESMTPSA id ib5sm15771717pbb.55.2014.06.27.11.04.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Jun 2014 11:04:42 -0700 (PDT) From: mathieu.poirier@linaro.org To: linus.walleij@linaro.org, will.deacon@arm.com, linux@arm.linux.org.uk, daniel.thompson@linaro.org, robherring2@gmail.com Cc: mathieu.poirier@linaro.org, arve@android.com, john.stultz@linaro.org, pratikp@codeaurora.org, varshney@ti.com, Al.Grant@arm.com, jonas.svennebring@avagotech.com, james.king@linaro.org, panchaxari.prasannamurthy@linaro.org, arnd@linaro.org, marcin.jabrzyk@gmail.com, r.sengupta@samsung.com, robbelibobban@gmail.com, Tony.Armitstead@arm.com, patches@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/9 v2] coresight-etb: add CoreSight ETB driver Date: Fri, 27 Jun 2014 12:04:16 -0600 Message-Id: <1403892261-25026-5-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1403892261-25026-1-git-send-email-mathieu.poirier@linaro.org> References: <1403892261-25026-1-git-send-email-mathieu.poirier@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mathieu.poirier@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Pratik Patel This driver manages CoreSight ETB (Embedded Trace Buffer) which acts as a circular buffer sink collecting generated trace data. Signed-off-by: Pratik Patel Signed-off-by: Panchaxari Prasannamurthy Signed-off-by: Mathieu Poirier --- drivers/coresight/Makefile | 3 +- drivers/coresight/coresight-etb.c | 557 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 559 insertions(+), 1 deletion(-) create mode 100644 drivers/coresight/coresight-etb.c diff --git a/drivers/coresight/Makefile b/drivers/coresight/Makefile index 540df99..8d4443b 100644 --- a/drivers/coresight/Makefile +++ b/drivers/coresight/Makefile @@ -3,4 +3,5 @@ # obj-$(CONFIG_CORESIGHT) += coresight.o obj-$(CONFIG_OF) += of_coresight.o -obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-tmc.o coresight-tpiu.o +obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-tmc.o coresight-tpiu.o \ + coresight-etb.o diff --git a/drivers/coresight/coresight-etb.c b/drivers/coresight/coresight-etb.c new file mode 100644 index 0000000..062d343 --- /dev/null +++ b/drivers/coresight/coresight-etb.c @@ -0,0 +1,557 @@ +/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-priv.h" + +#define ETB_RAM_DEPTH_REG (0x004) +#define ETB_STATUS_REG (0x00C) +#define ETB_RAM_READ_DATA_REG (0x010) +#define ETB_RAM_READ_POINTER (0x014) +#define ETB_RAM_WRITE_POINTER (0x018) +#define ETB_TRG (0x01C) +#define ETB_CTL_REG (0x020) +#define ETB_RWD_REG (0x024) +#define ETB_FFSR (0x300) +#define ETB_FFCR (0x304) +#define ETB_ITMISCOP0 (0xEE0) +#define ETB_ITTRFLINACK (0xEE4) +#define ETB_ITTRFLIN (0xEE8) +#define ETB_ITATBDATA0 (0xEEC) +#define ETB_ITATBCTR2 (0xEF0) +#define ETB_ITATBCTR1 (0xEF4) +#define ETB_ITATBCTR0 (0xEF8) + +/** register description **/ +/* STS - 0x00C */ +#define ETB_STATUS_RAM_FULL BIT(0) +/* CTL - 0x020 */ +#define ETB_CTL_CAPT_EN BIT(0) +/* FFCR - 0x304 */ +#define ETB_FFCR_EN_FTC BIT(0) +#define ETB_FFCR_FON_MAN BIT(6) +#define ETB_FFCR_STOP_FI BIT(12) +#define ETB_FFCR_STOP_TRIGGER BIT(13) + +#define ETB_FFCR_BIT 6 +#define ETB_FFSR_BIT 1 +#define ETB_FRAME_SIZE_WORDS 4 + +struct etb_drvdata { + void __iomem *base; + struct device *dev; + struct coresight_device *csdev; + struct miscdevice miscdev; + struct clk *clk; + spinlock_t spinlock; + bool reading; + atomic_t in_use; + u8 *buf; + u32 buffer_depth; + bool enable; + u32 trigger_cntr; +}; + +static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata) +{ + int ret; + u32 depth = 0; + + ret = clk_prepare_enable(drvdata->clk); + if (ret) + return ret; + + /* RO registers don't need locking */ + depth = cs_readl(drvdata->base, ETB_RAM_DEPTH_REG); + + clk_disable_unprepare(drvdata->clk); + return depth; +} + +static void etb_enable_hw(struct etb_drvdata *drvdata) +{ + int i; + u32 depth; + + CS_UNLOCK(drvdata->base); + + depth = drvdata->buffer_depth; + /* reset write RAM pointer address */ + cs_writel(drvdata->base, 0x0, ETB_RAM_WRITE_POINTER); + /* clear entire RAM buffer */ + for (i = 0; i < depth; i++) + cs_writel(drvdata->base, 0x0, ETB_RWD_REG); + + /* reset write RAM pointer address */ + cs_writel(drvdata->base, 0x0, ETB_RAM_WRITE_POINTER); + /* reset read RAM pointer address */ + cs_writel(drvdata->base, 0x0, ETB_RAM_READ_POINTER); + + cs_writel(drvdata->base, drvdata->trigger_cntr, ETB_TRG); + cs_writel(drvdata->base, + ETB_FFCR_EN_FTC | + ETB_FFCR_STOP_TRIGGER, + ETB_FFCR); + /* ETB trace capture enable */ + cs_writel(drvdata->base, ETB_CTL_CAPT_EN, ETB_CTL_REG); + + CS_LOCK(drvdata->base); +} + +static int etb_enable(struct coresight_device *csdev) +{ + struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret; + unsigned long flags; + + ret = clk_prepare_enable(drvdata->clk); + if (ret) + return ret; + + spin_lock_irqsave(&drvdata->spinlock, flags); + etb_enable_hw(drvdata); + drvdata->enable = true; + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + dev_info(drvdata->dev, "ETB enabled\n"); + return 0; +} + +static void etb_disable_hw(struct etb_drvdata *drvdata) +{ + int i; + u32 ffcr; + + CS_UNLOCK(drvdata->base); + + ffcr = cs_readl(drvdata->base, ETB_FFCR); + /* stop formatter when a stop has completed */ + ffcr |= ETB_FFCR_STOP_FI; + cs_writel(drvdata->base, ffcr, ETB_FFCR); + /* manually generate a flush of the system */ + ffcr |= ETB_FFCR_FON_MAN; + cs_writel(drvdata->base, ffcr, ETB_FFCR); + for (i = TIMEOUT_US; + BVAL(cs_readl(drvdata->base, ETB_FFCR), ETB_FFCR_BIT) != 0 + && i > 0; i--) + udelay(1); + WARN(i == 0, "timeout while flushing DRVDATA, ETB_FFCR: %#x\n", + cs_readl(drvdata->base, ETB_FFCR)); + + /* disable trace capture */ + cs_writel(drvdata->base, 0x0, ETB_CTL_REG); + for (i = TIMEOUT_US; + BVAL(cs_readl(drvdata->base, ETB_FFSR), ETB_FFSR_BIT) != 1 + && i > 0; i--) + udelay(1); + WARN(i == 0, "timeout while disabling DRVDATA, ETB_FFSR: %#x\n", + cs_readl(drvdata->base, ETB_FFSR)); + + CS_LOCK(drvdata->base); +} + +static void etb_dump_hw(struct etb_drvdata *drvdata) +{ + int i; + u8 *buf_ptr; + u32 read_data, depth; + u32 read_ptr, write_ptr; + u32 frame_off, frame_endoff; + + CS_UNLOCK(drvdata->base); + + read_ptr = cs_readl(drvdata->base, ETB_RAM_READ_POINTER); + write_ptr = cs_readl(drvdata->base, ETB_RAM_WRITE_POINTER); + + frame_off = write_ptr % ETB_FRAME_SIZE_WORDS; + frame_endoff = ETB_FRAME_SIZE_WORDS - frame_off; + if (frame_off) { + dev_err(drvdata->dev, + "write_ptr: %lu not aligned to formatter frame size\n", + (unsigned long)write_ptr); + dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n", + (unsigned long)frame_off, (unsigned long)frame_endoff); + write_ptr += frame_endoff; + } + + if ((cs_readl(drvdata->base, ETB_STATUS_REG) + & ETB_STATUS_RAM_FULL) == 0) + cs_writel(drvdata->base, 0x0, ETB_RAM_READ_POINTER); + else + cs_writel(drvdata->base, write_ptr, ETB_RAM_READ_POINTER); + + depth = drvdata->buffer_depth; + buf_ptr = drvdata->buf; + for (i = 0; i < depth; i++) { + read_data = cs_readl(drvdata->base, ETB_RAM_READ_DATA_REG); + *buf_ptr++ = read_data >> 0; + *buf_ptr++ = read_data >> 8; + *buf_ptr++ = read_data >> 16; + *buf_ptr++ = read_data >> 24; + } + + if (frame_off) { + buf_ptr -= (frame_endoff * 4); + for (i = 0; i < frame_endoff; i++) { + *buf_ptr++ = 0x0; + *buf_ptr++ = 0x0; + *buf_ptr++ = 0x0; + *buf_ptr++ = 0x0; + } + } + + cs_writel(drvdata->base, read_ptr, ETB_RAM_READ_POINTER); + + CS_LOCK(drvdata->base); +} + +static void etb_disable(struct coresight_device *csdev) +{ + struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + + spin_lock_irqsave(&drvdata->spinlock, flags); + etb_disable_hw(drvdata); + etb_dump_hw(drvdata); + drvdata->enable = false; + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + clk_disable_unprepare(drvdata->clk); + + dev_info(drvdata->dev, "ETB disabled\n"); +} + +static void etb_abort(struct coresight_device *csdev) +{ + struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + + spin_lock_irqsave(&drvdata->spinlock, flags); + etb_disable_hw(drvdata); + etb_dump_hw(drvdata); + drvdata->enable = false; + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + dev_info(drvdata->dev, "ETB aborted\n"); +} + +static const struct coresight_ops_sink etb_sink_ops = { + .enable = etb_enable, + .disable = etb_disable, + .abort = etb_abort, +}; + +static const struct coresight_ops etb_cs_ops = { + .sink_ops = &etb_sink_ops, +}; + +static void etb_dump(struct etb_drvdata *drvdata) +{ + unsigned long flags; + + spin_lock_irqsave(&drvdata->spinlock, flags); + if (drvdata->enable) { + etb_disable_hw(drvdata); + etb_dump_hw(drvdata); + etb_enable_hw(drvdata); + } + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + dev_info(drvdata->dev, "ETB dumped\n"); +} + +static int etb_open(struct inode *inode, struct file *file) +{ + struct etb_drvdata *drvdata = container_of(file->private_data, + struct etb_drvdata, miscdev); + + if (atomic_cmpxchg(&drvdata->in_use, 0, 1)) + return -EBUSY; + + dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__); + return 0; +} + +static ssize_t etb_read(struct file *file, char __user *data, + size_t len, loff_t *ppos) +{ + u32 depth; + struct etb_drvdata *drvdata = container_of(file->private_data, + struct etb_drvdata, miscdev); + + if (drvdata->reading == false) { + etb_dump(drvdata); + drvdata->reading = true; + } + + depth = drvdata->buffer_depth; + if (*ppos + len > depth * 4) + len = depth * 4 - *ppos; + + if (copy_to_user(data, drvdata->buf + *ppos, len)) { + dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__); + return -EFAULT; + } + + *ppos += len; + + dev_dbg(drvdata->dev, "%s: %d bytes copied, %d bytes left\n", + __func__, len, (int) (depth * 4 - *ppos)); + return len; +} + +static int etb_release(struct inode *inode, struct file *file) +{ + struct etb_drvdata *drvdata = container_of(file->private_data, + struct etb_drvdata, miscdev); + + drvdata->reading = false; + atomic_set(&drvdata->in_use, 0); + + dev_dbg(drvdata->dev, "%s: released\n", __func__); + return 0; +} + +static const struct file_operations etb_fops = { + .owner = THIS_MODULE, + .open = etb_open, + .read = etb_read, + .release = etb_release, + .llseek = no_llseek, +}; + +static ssize_t debugfs_status_show(struct seq_file *f, void *ptr) +{ + int ret; + unsigned long flags; + u32 etb_rdr, etb_sr, etb_rrp, etb_rwp; + u32 etb_trg, etb_cr, etb_ffsr, etb_ffcr; + struct etb_drvdata *drvdata = f->private; + + ret = clk_prepare_enable(drvdata->clk); + if (ret) + goto out; + + spin_lock_irqsave(&drvdata->spinlock, flags); + CS_UNLOCK(drvdata->base); + + etb_rdr = cs_readl(drvdata->base, ETB_RAM_DEPTH_REG); + etb_sr = cs_readl(drvdata->base, ETB_STATUS_REG); + etb_rrp = cs_readl(drvdata->base, ETB_RAM_READ_POINTER); + etb_rwp = cs_readl(drvdata->base, ETB_RAM_WRITE_POINTER); + etb_trg = cs_readl(drvdata->base, ETB_TRG); + etb_cr = cs_readl(drvdata->base, ETB_CTL_REG); + etb_ffsr = cs_readl(drvdata->base, ETB_FFSR); + etb_ffcr = cs_readl(drvdata->base, ETB_FFCR); + + CS_LOCK(drvdata->base); + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + clk_disable_unprepare(drvdata->clk); + + seq_printf(f, + "Depth:\t\t0x%x\n" + "Status:\t\t0x%x\n" + "RAM read ptr:\t0x%x\n" + "RAM wrt ptr:\t0x%x\n" + "Trigger cnt:\t0x%x\n" + "Control:\t0x%x\n" + "Flush status:\t0x%x\n" + "Flush ctrl:\t0x%x\n", + etb_rdr, etb_sr, etb_rrp, etb_rwp, + etb_trg, etb_cr, etb_ffsr, etb_ffcr); +out: + return 0; +} + +static int debugfs_status_show_open(struct inode *inode, struct file *file) +{ + return single_open(file, debugfs_status_show, inode->i_private); +} + +static const struct file_operations debugfs_status_ops = { + .open = debugfs_status_show_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static const struct coresight_ops_entry debugfs_status_entry = { + .name = "status", + .mode = S_IRUGO, + .ops = &debugfs_status_ops, +}; + +static ssize_t debugfs_trigger_cntr_get(void *data, u64 *val) +{ + struct etb_drvdata *drvdata = data; + + *val = drvdata->trigger_cntr; + return 0; +} + +static ssize_t debugfs_trigger_cntr_set(void *data, u64 val) +{ + struct etb_drvdata *drvdata = data; + + drvdata->trigger_cntr = val; + return 0; +} +CORESIGHT_DEBUGFS_ENTRY(debugfs_trigger_cntr, "trigger_cntr", + S_IRUGO | S_IWUSR, debugfs_trigger_cntr_get, + debugfs_trigger_cntr_set, "%llu\n"); + +static const struct coresight_ops_entry *etb_attr_grps[] = { + &debugfs_trigger_cntr_entry, + &debugfs_status_entry, + NULL, +}; + +static int etb_probe(struct amba_device *adev, const struct amba_id *id) +{ + int ret; + void __iomem *base; + struct device *dev = &adev->dev; + struct coresight_platform_data *pdata = NULL; + struct etb_drvdata *drvdata; + struct resource *res = &adev->res; + struct coresight_desc *desc; + struct device_node *np = adev->dev.of_node; + + if (np) { + pdata = of_get_coresight_platform_data(dev, np); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + adev->dev.platform_data = pdata; + } + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev = &adev->dev; + dev_set_drvdata(dev, drvdata); + + /* validity for the resource is already checked by the AMBA core */ + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + drvdata->base = base; + + spin_lock_init(&drvdata->spinlock); + + drvdata->clk = adev->pclk; + ret = clk_prepare_enable(drvdata->clk); + if (ret) + return ret; + + drvdata->buffer_depth = etb_get_buffer_depth(drvdata); + clk_disable_unprepare(drvdata->clk); + + if (drvdata->buffer_depth < 0) + return -EINVAL; + + drvdata->buf = devm_kzalloc(dev, + drvdata->buffer_depth * 4, GFP_KERNEL); + if (!drvdata->buf) + return -ENOMEM; + + desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); + if (!desc) + return -ENOMEM; + + desc->type = CORESIGHT_DEV_TYPE_SINK; + desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; + desc->ops = &etb_cs_ops; + desc->pdata = pdata; + desc->dev = dev; + desc->debugfs_ops = etb_attr_grps; + desc->owner = THIS_MODULE; + drvdata->csdev = coresight_register(desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + drvdata->miscdev.name = pdata->name; + drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; + drvdata->miscdev.fops = &etb_fops; + ret = misc_register(&drvdata->miscdev); + if (ret) + goto err_misc_register; + + dev_info(dev, "ETB initialized\n"); + return 0; + +err_misc_register: + coresight_unregister(drvdata->csdev); + return ret; +} + +static int etb_remove(struct amba_device *adev) +{ + struct etb_drvdata *drvdata = amba_get_drvdata(adev); + + misc_deregister(&drvdata->miscdev); + coresight_unregister(drvdata->csdev); + return 0; +} + +static struct amba_id etb_ids[] = { + { + .id = 0x0003b907, + .mask = 0x0003ffff, + }, + { 0, 0}, +}; + +static struct amba_driver etb_driver = { + .drv = { + .name = "coresight-etb", + .owner = THIS_MODULE, + }, + .probe = etb_probe, + .remove = etb_remove, + .id_table = etb_ids, +}; + +static int __init etb_init(void) +{ + return amba_driver_register(&etb_driver); +} +module_init(etb_init); + +static void __exit etb_exit(void) +{ + amba_driver_unregister(&etb_driver); +} +module_exit(etb_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("CoreSight Embedded Trace Buffer driver");