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[2001:1868:205::9]) by mx.google.com with ESMTPS id p13si8235941pdn.318.2014.07.09.23.57.23 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Jul 2014 23:57:23 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X58H7-0003aB-17; Thu, 10 Jul 2014 06:56:13 +0000 Received: from szxga01-in.huawei.com ([119.145.14.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X58G7-0001hA-LC for linux-arm-kernel@lists.infradead.org; Thu, 10 Jul 2014 06:55:13 +0000 Received: from 172.24.2.119 (EHLO SZXEML414-HUB.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id BYO22147; Thu, 10 Jul 2014 14:54:29 +0800 (CST) Received: from localhost (10.177.27.142) by SZXEML414-HUB.china.huawei.com (10.82.67.153) with Microsoft SMTP Server id 14.3.158.1; Thu, 10 Jul 2014 14:54:21 +0800 From: Zhen Lei To: Catalin Marinas , Will Deacon , linux-arm-kernel Subject: [PATCH v3 10/13] iommu/arm: Adjust code to reuse more Date: Thu, 10 Jul 2014 14:53:03 +0800 Message-ID: <1404975186-12032-11-git-send-email-thunder.leizhen@huawei.com> X-Mailer: git-send-email 1.8.4.msysgit.0 In-Reply-To: <1404975186-12032-1-git-send-email-thunder.leizhen@huawei.com> References: <1404975186-12032-1-git-send-email-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.27.142] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140709_235512_168194_EC781FD6 X-CRM114-Status: GOOD ( 13.51 ) X-Spam-Score: -1.4 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [119.145.14.64 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [119.145.14.64 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Zhen Lei X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: thunder.leizhen@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.177 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Limit smmu ias,oas,uas size is a common operation, the value of register MAIR0 should be consistent across all SMMUs. Signed-off-by: Zhen Lei --- drivers/iommu/arm-smmu-base.c | 20 ++++++++++++++++++++ drivers/iommu/arm-smmu.c | 27 ++++----------------------- drivers/iommu/arm-smmu.h | 7 +++++++ 3 files changed, 31 insertions(+), 23 deletions(-) -- 1.8.0 diff --git a/drivers/iommu/arm-smmu-base.c b/drivers/iommu/arm-smmu-base.c index 400de39..8013751 100644 --- a/drivers/iommu/arm-smmu-base.c +++ b/drivers/iommu/arm-smmu-base.c @@ -954,6 +954,26 @@ int arm_smmu_device_dt_probe(struct platform_device *pdev, return -ENOMEM; } + /* + * Stage-1 output limited by stage-2 input size due to pgd + * allocation (PTRS_PER_PGD). + */ +#ifdef CONFIG_64BIT + smmu->s1_output_size = min((u32)VA_BITS, smmu->s1_output_size); + smmu->input_size = min((u32)VA_BITS, smmu->input_size); +#else + smmu->s1_output_size = min(32U, smmu->s1_output_size); + smmu->input_size = 32; +#endif + + /* The stage-2 output mask is also applied for bypass */ + smmu->s2_output_size = min((u32)PHYS_MASK_SHIFT, smmu->s2_output_size); + + dev_notice(smmu->dev, + "\t%u-bit VA, %u-bit IPA, %u-bit PA\n", + smmu->input_size, + smmu->s1_output_size, smmu->s2_output_size); + parse_driver_options(smmu); if (smmu->version > 1 && diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index dbd9c60..6971e11 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -489,9 +489,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) /* MAIR0 (stage-1 only) */ if (stage1) { - reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) | - (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) | - (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV)); + reg = MAIR0_STAGE1; writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0); } @@ -828,30 +826,16 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); - /* - * Stage-1 output limited by stage-2 input size due to pgd - * allocation (PTRS_PER_PGD). - */ -#ifdef CONFIG_64BIT - smmu->s1_output_size = min((u32)VA_BITS, size); -#else - smmu->s1_output_size = min(32U, size); -#endif + smmu->s1_output_size = size; - /* The stage-2 output mask is also applied for bypass */ size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK); - smmu->s2_output_size = min((u32)PHYS_MASK_SHIFT, size); + smmu->s2_output_size = size; if (smmu->version == 1) { smmu->input_size = 32; } else { -#ifdef CONFIG_64BIT size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; - size = min((u32)VA_BITS, arm_smmu_id_size_to_bits(size)); -#else - size = 32; -#endif - smmu->input_size = size; + smmu->input_size = arm_smmu_id_size_to_bits(size); if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) || (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) || @@ -862,9 +846,6 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) } } - dev_notice(smmu->dev, - "\t%u-bit VA, %u-bit IPA, %u-bit PA\n", - smmu->input_size, smmu->s1_output_size, smmu->s2_output_size); return 0; } diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index fff2b98..3164ba78 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -72,6 +72,7 @@ #define RESUME_RETRY (0 << 0) #define RESUME_TERMINATE (1 << 0) +/* In SMMUv2, this register is named SMMU_CBn_TCR */ #define TTBCR_EAE (1 << 31) #define TTBCR_PASIZE_SHIFT 16 @@ -112,6 +113,12 @@ #define MAIR_ATTR_IDX_CACHE 1 #define MAIR_ATTR_IDX_DEV 2 +#define MAIR0_STAGE1 \ + ((MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) | \ + (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) | \ + (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV))) + + struct arm_smmu_smr { u8 idx; u16 mask;