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[2001:1868:205::9]) by mx.google.com with ESMTPS id zk3si47822160pbb.155.2014.07.09.23.57.12 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Jul 2014 23:57:12 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X58Gt-0003PC-O1; Thu, 10 Jul 2014 06:55:59 +0000 Received: from szxga01-in.huawei.com ([119.145.14.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X58G7-0001gf-LC for linux-arm-kernel@lists.infradead.org; Thu, 10 Jul 2014 06:55:13 +0000 Received: from 172.24.2.119 (EHLO szxeml406-hub.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id BYO22130; Thu, 10 Jul 2014 14:54:23 +0800 (CST) Received: from localhost (10.177.27.142) by szxeml406-hub.china.huawei.com (10.82.67.93) with Microsoft SMTP Server id 14.3.158.1; Thu, 10 Jul 2014 14:54:16 +0800 From: Zhen Lei To: Catalin Marinas , Will Deacon , linux-arm-kernel Subject: [PATCH v3 05/13] iommu/arm: Rename member "cbar" in struct arm_smmu_cfg to "type" Date: Thu, 10 Jul 2014 14:52:58 +0800 Message-ID: <1404975186-12032-6-git-send-email-thunder.leizhen@huawei.com> X-Mailer: git-send-email 1.8.4.msysgit.0 In-Reply-To: <1404975186-12032-1-git-send-email-thunder.leizhen@huawei.com> References: <1404975186-12032-1-git-send-email-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.27.142] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140709_235512_151025_6150220D X-CRM114-Status: GOOD ( 12.67 ) X-Spam-Score: -1.4 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [119.145.14.64 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [119.145.14.64 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Zhen Lei X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: thunder.leizhen@huawei.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Some SMMUs may not contain register CBAR, or the "type" field definition may be different. Signed-off-by: Zhen Lei --- drivers/iommu/arm-smmu-base.c | 8 ++++---- drivers/iommu/arm-smmu.c | 8 +++++--- drivers/iommu/arm-smmu.h | 11 ++++------- 3 files changed, 13 insertions(+), 14 deletions(-) -- 1.8.0 diff --git a/drivers/iommu/arm-smmu-base.c b/drivers/iommu/arm-smmu-base.c index c6824b5..0b02da8 100644 --- a/drivers/iommu/arm-smmu-base.c +++ b/drivers/iommu/arm-smmu-base.c @@ -240,13 +240,13 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, * We will likely want to change this if/when KVM gets * involved. */ - root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; + root_cfg->type = TYPE_S1_TRANS_S2_BYPASS; start = smmu->num_s2_context_banks; } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) { - root_cfg->cbar = CBAR_TYPE_S2_TRANS; + root_cfg->type = TYPE_S2_TRANS; start = 0; } else { - root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; + root_cfg->type = TYPE_S1_TRANS_S2_BYPASS; start = smmu->num_s2_context_banks; } @@ -633,7 +633,7 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu = root_cfg->smmu; unsigned long flags; - if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) { + if (root_cfg->type == TYPE_S2_TRANS) { stage = 2; output_mask = (1ULL << smmu->s2_output_size) - 1; } else { diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index d08149d..b9538f6 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -153,6 +153,8 @@ #define CBAR_S1_MEMATTR_SHIFT 12 #define CBAR_S1_MEMATTR_MASK 0xf #define CBAR_S1_MEMATTR_WB 0xf +#define CBAR_TYPE_SHIFT 16 +#define CBAR_TYPE_MASK 0x3 #define CBAR_IRPTNDX_SHIFT 24 #define CBAR_IRPTNDX_MASK 0xff @@ -244,7 +246,7 @@ static void arm_smmu_tlb_inv_context(struct arm_smmu_cfg *cfg) { struct arm_smmu_device *smmu = cfg->smmu; void __iomem *base = ARM_SMMU_GR0(smmu); - bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; + bool stage1 = cfg->type != TYPE_S2_TRANS; if (stage1) { base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); @@ -346,11 +348,11 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) gr0_base = ARM_SMMU_GR0(smmu); gr1_base = ARM_SMMU_GR1(smmu); - stage1 = root_cfg->cbar != CBAR_TYPE_S2_TRANS; + stage1 = root_cfg->type != TYPE_S2_TRANS; cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx); /* CBAR */ - reg = root_cfg->cbar; + reg = root_cfg->type << CBAR_TYPE_SHIFT; if (smmu->version == 1) reg |= root_cfg->irptndx << CBAR_IRPTNDX_SHIFT; diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h index ca35694..d66a8c4 100644 --- a/drivers/iommu/arm-smmu.h +++ b/drivers/iommu/arm-smmu.h @@ -68,12 +68,9 @@ #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ -#define CBAR_TYPE_SHIFT 16 -#define CBAR_TYPE_MASK 0x3 -#define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) -#define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) -#define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) -#define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) +#define TYPE_S2_TRANS 0 +#define TYPE_S1_TRANS_S2_BYPASS 1 +#define TYPE_S1_TRANS_S2_TRANS 3 #define RESUME_RETRY (0 << 0) #define RESUME_TERMINATE (1 << 0) @@ -189,7 +186,7 @@ struct arm_smmu_cfg { struct arm_smmu_device *smmu; u8 cbndx; u8 irptndx; - u32 cbar; + u32 type; pgd_t *pgd; }; #define INVALID_IRPTNDX 0xff