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[83.153.85.71]) by mx.google.com with ESMTPSA id gm2sm13080583wib.15.2014.09.08.13.30.22 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 08 Sep 2014 13:30:25 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, marc.zyngier@arm.com, christoffer.dall@linaro.org Subject: [PATCH] ARM/arm64: KVM: fix use of WnR bit in kvm_is_write_fault() Date: Mon, 8 Sep 2014 22:29:27 +0200 Message-Id: <1410208167-32532-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 1.8.3.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140908_133048_852921_E75689F2 X-CRM114-Status: GOOD ( 12.31 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.178 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [74.125.82.178 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: peter.maydell@linaro.org, lersek@redhat.com, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Ard Biesheuvel X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The ISS encoding for an exception from a Data Abort has a WnR bit[6] that indicates whether the Data Abort was caused by a read or a write instruction. While there are several fields in the encoding that are only valid if the ISV bit[24] is set, WnR is not one of them, so we can read it unconditionally. Signed-off-by: Ard Biesheuvel Acked-by: Laszlo Ersek --- This fixes an issue I observed with UEFI running under QEMU/KVM using NOR flash emulation and the upcoming KVM_CAP_READONLY_MEM support, where NOR flash reads were mistaken for NOR flash writes, resulting in all read accesses to go through the MMIO emulation layer. arch/arm/include/asm/kvm_mmu.h | 5 +---- arch/arm64/include/asm/kvm_mmu.h | 5 +---- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index 5cc0b0f5f72f..fad5648980ad 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -83,10 +83,7 @@ static inline bool kvm_is_write_fault(unsigned long hsr) unsigned long hsr_ec = hsr >> HSR_EC_SHIFT; if (hsr_ec == HSR_EC_IABT) return false; - else if ((hsr & HSR_ISV) && !(hsr & HSR_WNR)) - return false; - else - return true; + return hsr & HSR_WNR; } static inline void kvm_clean_pgd(pgd_t *pgd) diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h index 8e138c7c53ac..09fd9e4c13d8 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -100,10 +100,7 @@ static inline bool kvm_is_write_fault(unsigned long esr) if (esr_ec == ESR_EL2_EC_IABT) return false; - if ((esr & ESR_EL2_ISV) && !(esr & ESR_EL2_WNR)) - return false; - - return true; + return esr & ESR_EL2_WNR; } static inline void kvm_clean_pgd(pgd_t *pgd) {}