From patchwork Tue Oct 21 13:11:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 39139 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f198.google.com (mail-wi0-f198.google.com [209.85.212.198]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 2F127202DB for ; Tue, 21 Oct 2014 13:14:22 +0000 (UTC) Received: by mail-wi0-f198.google.com with SMTP id hi2sf936314wib.1 for ; Tue, 21 Oct 2014 06:14:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :in-reply-to:references:cc:precedence:list-id:list-unsubscribe :list-archive:list-post:list-help:list-subscribe:mime-version:sender :errors-to:x-original-sender:x-original-authentication-results :mailing-list:content-type:content-transfer-encoding; bh=FnakuY0+YZdoZOE7iP2TiPoQ4rrPIPqG05nOT4me7zA=; b=K9DabBoKnpFzHZUGemUvkV9++bI9JJkgldi4fekbCLZRr0Z/C0vsUAwQ/wwQaDdoGy y963ZTSZZzqlGHB50LI4/vLdt99YtzWteWhKd8UihlE2z5fjTnAwocZo1gZJFA4jF6WQ zucQsyoWpsNucfGkJZv1mxuQ7mJptPys/SZCckdM4REt6AjnSg6zmW2cmkcRe1TzU695 fQuXXUKOC9FsO7XDNL2Ojr8b0LCkB5bGyD9A7Nxv0WZEU7JnnL7m5Pyo/iQbTCaqTVUg 74LqIGn6ht6xhk0Nh1uZtu1354DdV6xaDVhylXDuiproHBF6JWrh4wwUW4wy7CAr/PoJ eMsA== X-Gm-Message-State: ALoCoQnzMGTBXKIYpEsCv3GSZzXCnnhDE2fAGcq8KVPU16BomuEzXjKOBKrX3Hf1Yv++ef4KRkOw X-Received: by 10.152.28.4 with SMTP id x4mr475531lag.7.1413897259686; Tue, 21 Oct 2014 06:14:19 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.27.41 with SMTP id q9ls50234lag.67.gmail; Tue, 21 Oct 2014 06:14:19 -0700 (PDT) X-Received: by 10.112.189.10 with SMTP id ge10mr34344117lbc.23.1413897259478; Tue, 21 Oct 2014 06:14:19 -0700 (PDT) Received: from mail-la0-f54.google.com (mail-la0-f54.google.com. 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[2001:1868:205::9]) by mx.google.com with ESMTPS id pt7si11110470pbc.92.2014.10.21.06.14.16 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Oct 2014 06:14:17 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XgZF3-0008Pt-Ol; Tue, 21 Oct 2014 13:12:49 +0000 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XgZEz-00089J-L9 for linux-arm-kernel@lists.infradead.org; Tue, 21 Oct 2014 13:12:46 +0000 Received: from leverpostej.cambridge.arm.com (leverpostej.cambridge.arm.com [10.1.205.151]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id s9LDBfwr016180; Tue, 21 Oct 2014 14:12:23 +0100 (BST) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/8] arm: perf: use IDR types for CPU PMUs Date: Tue, 21 Oct 2014 14:11:19 +0100 Message-Id: <1413897084-19715-4-git-send-email-mark.rutland@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1413897084-19715-1-git-send-email-mark.rutland@arm.com> References: <1413897084-19715-1-git-send-email-mark.rutland@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141021_061246_056722_D47669CA X-CRM114-Status: GOOD ( 12.30 ) X-Spam-Score: -6.4 (------) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-6.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.96.50 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: Mark Rutland , pawel.moll@arm.com, sboyd@codeaurora.org, punit.agrawal@arm.com, will.deacon@arm.com, drew.richardson@arm.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mark.rutland@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.54 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 For systems with heterogeneous CPUs (e.g. big.LITTLE systems) the PMUs can be different in each cluster, and not all events can be migrated between clusters. To allow userspace to deal with this, it must be possible to address each PMU independently. This patch changes PMUs to be registered with dynamic (IDR) types, allowing them to be targeted individually. Each PMU's type can be found in ${SYSFS_ROOT}/bus/event_source/devices/${PMU_NAME}/type. >From userspace, raw events can be targeted at a specific PMU: $ perf stat -e ${PMU_NAME}/config=V,config1=V1,.../ Doing this does not break existing tools which use existing perf types: when perf core can't find a PMU of matching type (in perf_init_event) it'll iterate over the set of all PMUs. If a compatible PMU exists, it'll be found eventually. If more than one compatible PMU exists, the event will be handled by whichever PMU happens to be earlier in the pmus list (which currently will be the last compatible PMU registered). Signed-off-by: Mark Rutland Reviewed-by: Will Deacon --- arch/arm/kernel/perf_event.c | 6 +++++- arch/arm/kernel/perf_event_cpu.c | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index ae96b98..f0bbd3d 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -77,8 +77,12 @@ armpmu_map_event(struct perf_event *event, u32 raw_event_mask) { u64 config = event->attr.config; + int type = event->attr.type; - switch (event->attr.type) { + if (type >= PERF_TYPE_MAX && type == event->pmu->type) + return armpmu_map_raw_event(raw_event_mask, config); + + switch (type) { case PERF_TYPE_HARDWARE: return armpmu_map_hw_event(event_map, config); case PERF_TYPE_HW_CACHE: diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c index 79c1cf4..ed7bb04f 100644 --- a/arch/arm/kernel/perf_event_cpu.c +++ b/arch/arm/kernel/perf_event_cpu.c @@ -311,7 +311,7 @@ static int cpu_pmu_device_probe(struct platform_device *pdev) } cpu_pmu_init(cpu_pmu); - ret = armpmu_register(cpu_pmu, PERF_TYPE_RAW); + ret = armpmu_register(cpu_pmu, -1); if (!ret) return 0;