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[209.132.180.67]) by mx.google.com with ESMTP id r15si4789466pdj.62.2014.10.24.10.53.04 for ; Fri, 24 Oct 2014 10:53:04 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756833AbaJXRwA (ORCPT + 26 others); Fri, 24 Oct 2014 13:52:00 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:55221 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756094AbaJXRv7 (ORCPT ); Fri, 24 Oct 2014 13:51:59 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s9OHpaXj020035; Fri, 24 Oct 2014 12:51:36 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9OHpa28003148; Fri, 24 Oct 2014 12:51:36 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Fri, 24 Oct 2014 12:51:36 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s9OHpYAH004463; Fri, 24 Oct 2014 12:51:35 -0500 From: Murali Karicheri To: , CC: Murali Karicheri Subject: [PATCH 3/4] ARM: keystone: dts: add DT bindings for PCI controller for port 0 Date: Fri, 24 Oct 2014 13:51:34 -0400 Message-ID: <1414173095-32511-4-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1414173095-32511-1-git-send-email-m-karicheri2@ti.com> References: <1414173095-32511-1-git-send-email-m-karicheri2@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: m-karicheri2@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.182 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add common DT bindings to support Port 0 Root Complex on all of the K2 SoCs that has Synopsis Designware based pcie h/w. Signed-off-by: Murali Karicheri CC : Santosh Shilimkar CC : Rob Herring CC : Pawel Moll CC : Mark Rutland CC : Ian Campbell CC : Kumar Gala CC : Russell King CC : devicetree@vger.kernel.org --- arch/arm/boot/dts/keystone.dtsi | 45 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 5d3e83f..87b2daa 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -285,5 +285,50 @@ #interrupt-cells = <1>; ti,syscon-dev = <&devctrl 0x2a0>; }; + + pcie@21800000 { + compatible = "ti,keystone-pcie", "snps,dw-pcie"; + clocks = <&clkpcie>; + clock-names = "pcie"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; + ranges = <0x81000000 0 0 0x23250000 0 0x4000 + 0x82000000 0 0x50000000 0x50000000 0 0x10000000>; + + device_type = "pci"; + num-lanes = <2>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, // INT A + <0 0 0 2 &pcie_intc0 1>, // INT B + <0 0 0 3 &pcie_intc0 2>, // INT C + <0 0 0 4 &pcie_intc0 3>; // INT D + + pcie_msi_intc0: msi-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + pcie_intc0: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + }; }; };