From patchwork Wed May 6 15:27:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 48054 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f200.google.com (mail-wi0-f200.google.com [209.85.212.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id E247220553 for ; Wed, 6 May 2015 15:28:23 +0000 (UTC) Received: by wixv7 with SMTP id v7sf6884816wix.0 for ; Wed, 06 May 2015 08:28:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=haxTNHm/7lPBM49CRdSoR7HsiifflQHLaCGSUIMQnVo=; b=V7XasUqnVbk6qvBm8U37wehDPX3RQzVz4OC7BI74kfotsQdbhHo/pHF5EpKKEKQS6g dzxmJm6Mf7kjjrnT52UEHRzmZ4/8i8TRB7GXo6mWt/vKu8TJPoY6rnwzm6xNJDleCB/4 b4w1RzyrN+PG5fFczozIVasbg4h277hR1C2noa5SaJsB5vMj0V1pdckLy2Pv4OgfD9KS 6VlsnXQ1MDmoeQE3EfZzLHQyh/AoXDeSgKnp7W5frjJu8yKZ8MJjxl6d5D8+S2A2t6SZ SLJYuWk/iuY6fsc/jwSp0PmHjPNTDG+hCQNNL+p5mUxq9bCB4efwFd2uCjn1d+XeC/ZX z2gw== X-Gm-Message-State: ALoCoQlaVFiIFCigthM5xgMy23+aIoYWOptRf8S5IZOiEpZ7KQfXcUPrZgKrx2WHXTsNNuBAxjpS X-Received: by 10.112.42.236 with SMTP id r12mr26278309lbl.2.1430926103221; Wed, 06 May 2015 08:28:23 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.29.36 with SMTP id g4ls71135lah.33.gmail; Wed, 06 May 2015 08:28:23 -0700 (PDT) X-Received: by 10.112.137.1 with SMTP id qe1mr9838387lbb.22.1430926103040; Wed, 06 May 2015 08:28:23 -0700 (PDT) Received: from mail-lb0-f174.google.com (mail-lb0-f174.google.com. [209.85.217.174]) by mx.google.com with ESMTPS id j2si14923614lbd.98.2015.05.06.08.28.22 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 May 2015 08:28:22 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.174 as permitted sender) client-ip=209.85.217.174; Received: by lbbzk7 with SMTP id zk7so10393088lbb.0 for ; Wed, 06 May 2015 08:28:22 -0700 (PDT) X-Received: by 10.152.29.161 with SMTP id l1mr28232711lah.76.1430926102889; Wed, 06 May 2015 08:28:22 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.67.65 with SMTP id l1csp2921900lbt; Wed, 6 May 2015 08:28:21 -0700 (PDT) X-Received: by 10.70.134.198 with SMTP id pm6mr62599108pdb.17.1430926099155; Wed, 06 May 2015 08:28:19 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bs3si29447640pdb.245.2015.05.06.08.28.18; Wed, 06 May 2015 08:28:19 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752977AbbEFP2L (ORCPT + 29 others); Wed, 6 May 2015 11:28:11 -0400 Received: from mail-pd0-f170.google.com ([209.85.192.170]:35691 "EHLO mail-pd0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752786AbbEFP2C (ORCPT ); Wed, 6 May 2015 11:28:02 -0400 Received: by pdbqd1 with SMTP id qd1so12812294pdb.2 for ; Wed, 06 May 2015 08:28:02 -0700 (PDT) X-Received: by 10.70.130.198 with SMTP id og6mr61604168pdb.153.1430926082149; Wed, 06 May 2015 08:28:02 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by mx.google.com with ESMTPSA id fp3sm2221174pdb.52.2015.05.06.08.27.57 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 06 May 2015 08:28:01 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Cc: linux-arm-kernel@lists.infradead.org, linux-api@vger.kernel.org, linux-kernel@vger.kernel.org, kaixu.xia@linaro.org, zhang.chunyan@linaro.org, mathieu.poirier@linaro.org Subject: [PATCH v3 02/11] coresight-etm4x: Controls pertaining to tracer configuration Date: Wed, 6 May 2015 09:27:18 -0600 Message-Id: <1430926047-9125-3-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430926047-9125-1-git-send-email-mathieu.poirier@linaro.org> References: <1430926047-9125-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mathieu.poirier@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Pratik Patel Tracers can be configured with various options at synthesis time and knowing what resources are available is important for SW configuration purposes. As such adding RO sysfs entries for characteristics related to the tracer implementation. Signed-off-by: Pratik Patel Signed-off-by: Mathieu Poirier --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 61 +++++++++++ drivers/hwtracing/coresight/coresight-etm4x.c | 117 +++++++++++++++++++++ 2 files changed, 178 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index a4b623871ca0..0f579eb24631 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -26,3 +26,64 @@ Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier Description: (R) Provides value of all the ID registers (TRCIDRx). + +What: /sys/bus/coresight/devices/.etm/nr_pe_cmp +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of PE comparator inputs that are + available for tracing. + +What: /sys/bus/coresight/devices/.etm/nr_addr_cmp +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of address comparator pairs that are + available for tracing. + +What: /sys/bus/coresight/devices/.etm/nr_cntr +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of counters that are available for + tracing. + +What: /sys/bus/coresight/devices/.etm/nr_ext_inp +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates how many external inputs are implemented. + +What: /sys/bus/coresight/devices/.etm/numcidc +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of Context ID comparators that are + available for tracing. + +What: /sys/bus/coresight/devices/.etm/numvmidc +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of VMID comparators that are available + for tracing. + +What: /sys/bus/coresight/devices/.etm/nrseqstate +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of sequencer states that are implemented. + +What: /sys/bus/coresight/devices/.etm/nr_resource +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of resource selection pairs that are + available for tracing. + +What: /sys/bus/coresight/devices/.etm/nr_ss_cmp +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Indicates the number of single-shot comparator controls that + are available for tracing. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index db0bea4d4661..c7421f319350 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -268,6 +268,114 @@ static const struct coresight_ops etm4_cs_ops = { .source_ops = &etm4_source_ops, }; +static ssize_t nr_pe_cmp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_pe_cmp; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_pe_cmp); + +static ssize_t nr_addr_cmp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_addr_cmp; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_addr_cmp); + +static ssize_t nr_cntr_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_cntr; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_cntr); + +static ssize_t nr_ext_inp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_ext_inp; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_ext_inp); + +static ssize_t numcidc_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->numcidc; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(numcidc); + +static ssize_t numvmidc_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->numvmidc; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(numvmidc); + +static ssize_t nrseqstate_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nrseqstate; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nrseqstate); + +static ssize_t nr_resource_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_resource; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_resource); + +static ssize_t nr_ss_cmp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + unsigned long val; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + val = drvdata->nr_ss_cmp; + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} +static DEVICE_ATTR_RO(nr_ss_cmp); + static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -412,6 +520,15 @@ static ssize_t trcidr_show(struct device *dev, static DEVICE_ATTR_RO(trcidr); static struct attribute *coresight_etmv4_attrs[] = { + &dev_attr_nr_pe_cmp.attr, + &dev_attr_nr_addr_cmp.attr, + &dev_attr_nr_cntr.attr, + &dev_attr_nr_ext_inp.attr, + &dev_attr_numcidc.attr, + &dev_attr_numvmidc.attr, + &dev_attr_nrseqstate.attr, + &dev_attr_nr_resource.attr, + &dev_attr_nr_ss_cmp.attr, &dev_attr_status.attr, &dev_attr_mgmt.attr, &dev_attr_trcidr.attr,