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[82.45.1.190]) by mx.google.com with ESMTPSA id j7sm14695054wjz.11.2015.06.10.07.04.25 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 10 Jun 2015 07:04:25 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, srinivas.kandagatla@gmail.com, maxime.coquelin@st.com, patrice.chotard@st.com Cc: peter.griffin@linaro.org, lee.jones@linaro.org, devicetree@vger.kernel.org, hugues.fruchet@st.com Subject: [PATCH 6/9] ARM: STi: DT: Add STiH407 family tsin5 pinctrl configuration Date: Wed, 10 Jun 2015 15:04:03 +0100 Message-Id: <1433945046-19855-7-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1433945046-19855-1-git-send-email-peter.griffin@linaro.org> References: <1433945046-19855-1-git-send-email-peter.griffin@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.griffin@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.52 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , tsin5 can only be configured for serial data transfer. However depending on board design, two alternate tsin5 pin configurations are available, both in pin-controller-front0. pinctrl_tsin5_serial_alt1 is brought out on B2120 reference design as TSD on NIMB slot of the B2004A daughter board. Signed-off-by: Peter Griffin --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index 702f42d..87d0722 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -546,6 +546,27 @@ }; }; }; + + tsin5 { + pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 { + st,pins { + DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 { + st,pins { + DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>; + CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>; + VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; + ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; + PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; + }; + }; + }; }; pin-controller-front1 {