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[82.45.1.190]) by smtp.gmail.com with ESMTPSA id c3sm4230830wja.3.2015.07.08.09.11.33 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Jul 2015 09:11:34 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, srinivas.kandagatla@gmail.com, maxime.coquelin@st.com, patrice.chotard@st.com, vinod.koul@intel.com, dan.j.williams@intel.com Subject: [PATCH 1/7] dmaengine: st_fdma: Add STMicroelectronics FDMA DT binding documentation Date: Wed, 8 Jul 2015 17:11:22 +0100 Message-Id: <1436371888-27863-2-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1436371888-27863-1-git-send-email-peter.griffin@linaro.org> References: <1436371888-27863-1-git-send-email-peter.griffin@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150708_091155_031143_874A765E X-CRM114-Status: GOOD ( 16.18 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.175 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.212.175 listed in wl.mailspike.net] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: peter.griffin@linaro.org, devicetree@vger.kernel.org, lee.jones@linaro.org, dmaengine@vger.kernel.org, ludovic.barre@st.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.griffin@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 This patch adds the DT binding documentation for the FDMA constroller found on STi based chipsets from STMicroelectronics. Signed-off-by: Ludovic Barre Signed-off-by: Peter Griffin --- Documentation/devicetree/bindings/dma/st_fdma.txt | 76 +++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/st_fdma.txt diff --git a/Documentation/devicetree/bindings/dma/st_fdma.txt b/Documentation/devicetree/bindings/dma/st_fdma.txt new file mode 100644 index 0000000..1ec7470 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/st_fdma.txt @@ -0,0 +1,76 @@ +* STMicroelectronics Flexible Direct Memory Access Device Tree bindings + +The FDMA is a general-purpose direct memory access controller capable of +supporting 16 independent DMA channels. It accepts up to 32 DMA requests. +The FDMA is based on a Slim processor which require a firmware. + +* FDMA Controller + +Required properties: +- compatible : Should be "st,fdma_mpe31" +- reg : Should contain DMA registers location and length +- interrupts : Should contain one interrupt shared by all channel +- dma-channels : Number of channels supported by the controller +- #dma-cells : Must be <3>. +- st,fw-name : Should contain the name of the firmware to be loaded +- clocks : Must contain an entry for each name in clock-names +- clock-names : Must contain "fdma_slim, fdma_hi, fdma_low, fdma_ic" entries +See: Documentation/devicetree/bindings/clock/clock-bindings.txt + + +Example: + + fdma1: fdma-app@1 { + compatible = "st,fdma_mpe31"; + reg = <0x8e40000 0x20000>; + interrupts = ; + dma-channels = <16>; + #dma-cells = <3>; + st,fw-name = "fdma_STiH407_1.elf"; + clocks = <&CLK_S_C0_FLEXGEN CLK_FDMA>, + <&CLK_S_C0_FLEXGEN CLK_TX_ICN_DMU>, + <&CLK_S_C0_FLEXGEN CLK_TX_ICN_DMU>, + <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>; + clock-names = "fdma_slim", + "fdma_hi", + "fdma_low", + "fdma_ic"; + +* DMA client + +Required properties: +- dmas: Comma separated list of dma channel requests +- dma-names: Names of the aforementioned requested channels + +Each dmas request consists of 4 cells: +1. A phandle pointing to the FDMA controller +2. The request line number +3. A 32bit mask specifying (see include/linux/platform_data/dma-st-fdma.h) + -bit 2-0: Holdoff value, dreq will be masked for + 0x0: 0-0.5us + 0x1: 0.5-1us + 0x2: 1-1.5us + -bit 17: data swap + 0x0: disabled + 0x1: enabled + -bit 21: Increment Address + 0x0: no address increment between transfers + 0x1: increment address between transfers + -bit 22: 2 STBus Initiator Coprocessor interface + 0x0: high priority port + 0x1: low priority port +4. transfers type + 0 free running + 1 paced + +Example: + + snd_uni_player2: snd-uni-player@2 { + compatible = "st,snd_uni_player"; + status = "okay"; + reg = <0x8D82000 0x158>; + interrupts = ; + version = <5>; + dmas = <&fdma0 4 0 1>; + dma-names = "tx"; + description = "Uni Player #2 (DAC)";