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[82.45.1.190]) by smtp.gmail.com with ESMTPSA id c3sm4230830wja.3.2015.07.08.09.11.43 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Jul 2015 09:11:43 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, srinivas.kandagatla@gmail.com, maxime.coquelin@st.com, patrice.chotard@st.com, vinod.koul@intel.com, dan.j.williams@intel.com Subject: [PATCH 5/7] ARM: STi: DT: STiH407: Add FDMA driver and xbar driver dt nodes. Date: Wed, 8 Jul 2015 17:11:26 +0100 Message-Id: <1436371888-27863-6-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1436371888-27863-1-git-send-email-peter.griffin@linaro.org> References: <1436371888-27863-1-git-send-email-peter.griffin@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150708_091207_693265_04AD3490 X-CRM114-Status: GOOD ( 11.52 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.43 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [74.125.82.43 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: peter.griffin@linaro.org, devicetree@vger.kernel.org, lee.jones@linaro.org, dmaengine@vger.kernel.org, ludovic.barre@st.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.griffin@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 These nodes are required to get the fdma and xbar driver working on STiH407 based silicon. Signed-off-by: Peter Griffin --- arch/arm/boot/dts/stih407-family.dtsi | 59 +++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 838b812..b6d9e20 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -565,5 +565,64 @@ <&phy_port2 PHY_TYPE_USB3>; }; }; + + xbar0: fdma-xbar-mpe@0 { + compatible = "st,fdma-xbar-1.0"; + reg = <0x8e80000 0x1000>; + dma-requests = <79>; + #st,fdma-xbar-cells = <1>; + }; + + fdma0: fdma-audio@0 { + compatible = "st,fdma_mpe31"; + reg = <0x8e20000 0x20000>; + interrupts = ; + dma-channels = <16>; + #dma-cells = <3>; + st,fw-name = "fdma_STiH407_0.elf"; + clocks = <&clk_s_c0_flexgen CLK_FDMA>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "fdma_slim", + "fdma_hi", + "fdma_low", + "fdma_ic"; + }; + + fdma1: fdma-app@1 { + compatible = "st,fdma_mpe31"; + reg = <0x8e40000 0x20000>; + interrupts = ; + dma-channels = <16>; + #dma-cells = <3>; + st,fdma-xbar = <&xbar0 0>; + st,fw-name = "fdma_STiH407_1.elf"; + clocks = <&clk_s_c0_flexgen CLK_FDMA>, + <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, + <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "fdma_slim", + "fdma_hi", + "fdma_low", + "fdma_ic"; + }; + + fdma2: fdma-free_running@2 { + compatible = "st,fdma_mpe31"; + reg = <0x8e60000 0x20000>; + interrupts = ; + dma-channels = <16>; + #dma-cells = <3>; + st,fw-name = "fdma_STiH407_2.elf"; + clocks = <&clk_s_c0_flexgen CLK_FDMA>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>; + clock-names = "fdma_slim", + "fdma_hi", + "fdma_low", + "fdma_ic"; + }; }; };