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[209.132.180.67]) by mx.google.com with ESMTP id 16si7549097ion.57.2015.09.18.09.33.41; Fri, 18 Sep 2015 09:33:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932155AbbIRQdZ (ORCPT + 30 others); Fri, 18 Sep 2015 12:33:25 -0400 Received: from mail-pa0-f49.google.com ([209.85.220.49]:34709 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754615AbbIRQ1J (ORCPT ); Fri, 18 Sep 2015 12:27:09 -0400 Received: by padhy16 with SMTP id hy16so55268002pad.1 for ; Fri, 18 Sep 2015 09:27:08 -0700 (PDT) X-Received: by 10.68.68.233 with SMTP id z9mr8205352pbt.132.1442593627764; Fri, 18 Sep 2015 09:27:07 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id la4sm9847027pbc.76.2015.09.18.09.27.06 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Sep 2015 09:27:07 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net Cc: adrian.hunter@intel.com, zhang.chunyan@linaro.org, mike.leach@arm.com, tor@ti.com, al.grant@arm.com, pawel.moll@arm.com, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 04/20] coresight: etm3x: using chip logic to start/stop traces Date: Fri, 18 Sep 2015 10:26:18 -0600 Message-Id: <1442593594-10665-5-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> References: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mathieu.poirier@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.171 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Driving the external ETMEN pins to start and stop trace collection isn't reliable when doing rapid, successive trace collection runs. Using the internal event enable register logic to control tracing is much more dependable. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm3x.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 4ce9cfc06e93..3cdf0bcddb41 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -323,6 +323,7 @@ static void etm_configure_cpu(void *info) etmcr = etm_readl(drvdata, ETMCR); etmcr |= drvdata->port_size; + etmcr |= ETMCR_ETM_EN; etm_writel(drvdata, drvdata->ctrl | etmcr, ETMCR); etm_writel(drvdata, drvdata->trigger_event, ETMTRIGGER); etm_writel(drvdata, drvdata->startstop_ctrl, ETMTSSCR); @@ -397,7 +398,7 @@ static bool etm_is_enabled(struct coresight_device *csdev) */ static int etm_trace_enable(struct coresight_device *csdev, bool enable) { - u32 etmcr; + u32 etmteevr; struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); WARN_ON(drvdata->cpu != smp_processor_id()); @@ -410,13 +411,16 @@ static int etm_trace_enable(struct coresight_device *csdev, bool enable) CS_UNLOCK(drvdata->base); etm_set_prog(drvdata); - etmcr = etm_readl(drvdata, ETMCR); - - enable ? (etmcr |= ETMCR_ETM_EN) : - (etmcr &= ~ETMCR_ETM_EN); - - etm_writel(drvdata, ETMCR_ETM_EN | etmcr, ETMCR); + etmteevr = etm_readl(drvdata, ETMTEEVR); + if (enable) { + /* boolean function bits all set to '0' selects resource A */ + etmteevr &= ~(BIT(16) | BIT(15) | BIT(14)); + } else { + /* boolean function bit 14 negate resource selection A */ + etmteevr |= BIT(14); + } + etm_writel(drvdata, etmteevr, ETMTEEVR); etm_clr_prog(drvdata); CS_LOCK(drvdata->base);