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[2001:1868:205::9]) by mx.google.com with ESMTPS id fo1si34849994pbb.144.2015.11.02.04.59.23 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 02 Nov 2015 04:59:24 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org; dkim=neutral (body hash did not verify) header.i=@linaro_org.20150623.gappssmtp.com Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZtEgh-0000YK-TI; Mon, 02 Nov 2015 12:58:15 +0000 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZtEgS-0000H0-OI for linux-arm-kernel@lists.infradead.org; Mon, 02 Nov 2015 12:58:02 +0000 Received: by wmec75 with SMTP id c75so59596084wme.1 for ; Mon, 02 Nov 2015 04:57:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro_org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hSh6BotAemxXjD2tC63uT4S6GsLXKG2Mh3rjr18nlyo=; b=CPXbL6dwh/B7sOwoFXFB2TWBV8An6PTgXVRJNqzi9wHtJf1nfInJ+c7FVw5Vxiq6OQ w/MGQpbErVrcelwb86XPyVMGkd7ei8WBH8Hjo7/EQAKgv7SefbjDnmMDlOR7l8phpel5 cISB1Y5tSEuPsRX9t2+jOeodykKhUkDx/9FGAV3lZsCODzK92PLPT6uH+aJphOzpT7bM VS97podbjSm24wvrU4bAy+zqYvChi+TiaVR0Lsvfn6kpOw+504I1ODYnzGDn7/mrA4H6 svx1SJU69RMI5pDVAvkBk3G4BMH6S42rjW5iyMNFxKyTkwkza06f9AWtcMgXogcOYwfA sihw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hSh6BotAemxXjD2tC63uT4S6GsLXKG2Mh3rjr18nlyo=; b=nCzSn3VqiQ8OYBUgCWMSljc1hPlZdjakXEPzDnUES+hGHRPkfRqCIQmd157x5BRSMo Rafb3125iOxjlGvCtGtXti5IxDsqLHtzHC78PDB6/opwg6He1c0Pnu/X3ekatYTpEouc 6AayveqpOVGKnS9Y5+oWb7po1m7xwoY2c8ngAfTjkJu7E6L+wYtGxNZFkd8phHB+FHWd uSQXsyWip+apsY7iuvwzYxAzlAboNnmVZY0nJUn4gF1pV7DGZnCaVsC8/3prgAxscRax S7LEUMnEkPCuYmkBLPGFt8xzYi9XKHeoofTFj2Zjxx6/Lfdd8i5IAZ8zJna57ujFdTzu VEKw== X-Gm-Message-State: ALoCoQmp8IAzThSMrXe1VWD3nPwm8fha3uxB7wxGW2Cqh+2hXz88IVthULVNbUvdTpeUJEJ0kSvi X-Received: by 10.28.11.71 with SMTP id 68mr14213438wml.77.1446469059043; Mon, 02 Nov 2015 04:57:39 -0800 (PST) Received: from localhost.localdomain ([78.210.255.2]) by smtp.gmail.com with ESMTPSA id it4sm22263633wjb.0.2015.11.02.04.57.37 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Nov 2015 04:57:38 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Subject: [PATCH 03/22] clocksource/drivers/rockchip: Make the driver more compatible Date: Mon, 2 Nov 2015 13:56:31 +0100 Message-Id: <1446469011-22710-3-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1446469011-22710-1-git-send-email-daniel.lezcano@linaro.org> References: <1446469011-22710-1-git-send-email-daniel.lezcano@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151102_045801_136120_381AA53A X-CRM114-Status: GOOD ( 13.63 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [2a00:1450:400c:c09:0:0:0:230 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Heiko Stuebner , arnd@arndb.de, linux-kernel@vger.kernel.org, "open list:ARM/Rockchip SoC..." , john.stultz@linaro.org, "moderated list:ARM/Rockchip SoC..." , Caesar Wang MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org From: Caesar Wang Build the arm64 SoCs (e.g.: RK3368) on Rockchip platform, There are some failure with build up on timer driver for rockchip. Says: /tmp/ccdAnNy5.s:47: Error: missing immediate expression at operand 1 -- `dsb` ... The problem was different semantics of dsb on btw arm32 and arm64, Here we can convert the dsb with insteading of dsb(sy).The "sy" param is the default which you are allow to omit, so on arm32 dsb()and dsb(sy) are the same. Signed-off-by: Caesar Wang Signed-off-by: Daniel Lezcano --- drivers/clocksource/rockchip_timer.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c index d3c1742..724c321 100644 --- a/drivers/clocksource/rockchip_timer.c +++ b/drivers/clocksource/rockchip_timer.c @@ -49,14 +49,14 @@ static inline void __iomem *rk_base(struct clock_event_device *ce) static inline void rk_timer_disable(struct clock_event_device *ce) { writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG); - dsb(); + dsb(sy); } static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags) { writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags, rk_base(ce) + TIMER_CONTROL_REG); - dsb(); + dsb(sy); } static void rk_timer_update_counter(unsigned long cycles, @@ -64,13 +64,13 @@ static void rk_timer_update_counter(unsigned long cycles, { writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0); writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1); - dsb(); + dsb(sy); } static void rk_timer_interrupt_clear(struct clock_event_device *ce) { writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS); - dsb(); + dsb(sy); } static inline int rk_timer_set_next_event(unsigned long cycles,