From patchwork Thu Nov 19 14:54:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Auger Eric X-Patchwork-Id: 57011 Delivered-To: patches@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp3227277lbb; Thu, 19 Nov 2015 06:54:45 -0800 (PST) X-Received: by 10.194.24.38 with SMTP id r6mr8680739wjf.5.1447944869423; Thu, 19 Nov 2015 06:54:29 -0800 (PST) Return-Path: Received: from mail-wm0-x22c.google.com (mail-wm0-x22c.google.com. [2a00:1450:400c:c09::22c]) by mx.google.com with ESMTPS id h125si1029518wme.33.2015.11.19.06.54.29 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Nov 2015 06:54:29 -0800 (PST) Received-SPF: pass (google.com: domain of eric.auger@linaro.org designates 2a00:1450:400c:c09::22c as permitted sender) client-ip=2a00:1450:400c:c09::22c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of eric.auger@linaro.org designates 2a00:1450:400c:c09::22c as permitted sender) smtp.mailfrom=eric.auger@linaro.org; dkim=pass header.i=@linaro-org.20150623.gappssmtp.com Received: by wmww144 with SMTP id w144so241836168wmw.1 for ; Thu, 19 Nov 2015 06:54:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ezqz8l7IGUP9cpGuSc55Luc9ehhyYR+qEtGB8L2vzXE=; b=bHo5VDtt1yu2sEtGqiz4gi9gwEQthA+IDJtiw0yN1mhFQQDz9VW4VuEFhH6RIwFVIr N284z8IpS/1AcSOthGKszO8A1qW0GVcm1PZh5n/S/90ntE7Oi1p09z+L2bk7+lt7UGBY TSdgjxcCnpDt1o6M6dgnpAqoZH/KuxLPrMbepK5Ppdaxz8qLSaA/Asb6lE+ARjFcxngT L/1XSYf9w8IvdVkgW/LXtB1ZHwadVqpOd+ec0gsggdS1jrQaWQmethBbSqAGWXzvpmvF R1wi1L6e4Man2tsYho9g+NldPB8KtsLLvjWY1Ue9BkEwZwi8h/ke2FLAZA5z0XNQyNVB uYiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ezqz8l7IGUP9cpGuSc55Luc9ehhyYR+qEtGB8L2vzXE=; b=ZopDrnVknoiVARdThAJor1xQa0bwbsd4F81AvpDNoOJAXp1lee7Got/PDLxfUmfY9J xGvG5QjQKVjVn4tUq0JQ9NPEuBOfoHVXRAKlHVSQ2gAKcfGhax2Uu5K5KTE4WXk6fZwo UFN9Re3g6NIjM7hOA3KBD42eBinNgZteolAeCo75yfcUrWPfCWRmtfuAjROHFUM6sD16 mbheZQPXmjoauPKkrhe624SdcEdqUrPxy87mwDA4QQgxM8JKK2LTufLaNREHFaEGgOGD 4bVAQBiardQ7yqNii17OXe8ulJHDTRQEThlLgNy8g+7zvtjiTEpC3+1BnQd6KjXtTI75 574g== X-Gm-Message-State: ALoCoQkuCMdSb0nbGtn7XNfRwodMHmGMsD0Mi8V3Ot5XbJ9uVhCsMiiqthsXstefJ2Ckt3W6E4ja X-Received: by 10.28.142.205 with SMTP id q196mr17341802wmd.42.1447944869228; Thu, 19 Nov 2015 06:54:29 -0800 (PST) Return-Path: Received: from new-host-3.home (LMontsouris-657-1-37-90.w80-11.abo.wanadoo.fr. [80.11.198.90]) by smtp.gmail.com with ESMTPSA id h67sm34493865wmf.17.2015.11.19.06.54.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 19 Nov 2015 06:54:28 -0800 (PST) From: Eric Auger To: eric.auger@st.com, eric.auger@linaro.org, alex.williamson@redhat.com, b.reynal@virtualopensystems.com, christoffer.dall@linaro.org, marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Cc: andre.przywara@arm.com, linux-kernel@vger.kernel.org, patches@linaro.org Subject: [PATCH v4 11/13] KVM: arm/arm64: vgic: implement clear active for non shared mapped IRQ Date: Thu, 19 Nov 2015 14:54:01 +0000 Message-Id: <1447944843-17731-12-git-send-email-eric.auger@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1447944843-17731-1-git-send-email-eric.auger@linaro.org> References: <1447944843-17731-1-git-send-email-eric.auger@linaro.org> When disabling a non shared mapped IRQs, we must manually deactivate the corresponding physical IRQ on top of removing the active state from the distributor. Signed-off-by: Eric Auger --- virt/kvm/arm/vgic.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index bd500b4..98ae15f 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -604,14 +604,34 @@ bool vgic_handle_clear_active_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio, phys_addr_t offset, int vcpu_id) { - u32 *reg; + u32 *reg, orig, cleared; struct vgic_dist *dist = &kvm->arch.vgic; + struct kvm_vcpu *vcpu = kvm_get_vcpu(kvm, vcpu_id); + unsigned int i; reg = vgic_bitmap_get_reg(&dist->irq_active, vcpu_id, offset); + orig = *reg; vgic_reg_access(mmio, reg, offset, ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT); if (mmio->is_write) { + cleared = orig ^ *reg; + + for (i = 0; i < 32; i++) { + struct irq_phys_map *map; + unsigned int irq_num; + + if (!(cleared && (1 << i))) + continue; + irq_num = (offset * 8) + i; + map = vgic_irq_map_search(vcpu, irq_num); + if (!map || (map && map->shared)) + continue; + irq_set_irqchip_state(map->irq, + IRQCHIP_STATE_ACTIVE, + false); + } + vgic_update_state(kvm); return true; }