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[2001:1868:205::9]) by mx.google.com with ESMTPS id z26si10807374pfa.30.2016.02.03.10.43.10 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Feb 2016 10:43:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org; dkim=neutral (body hash did not verify) header.i=@linaro.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aR2NU-0002Vt-KQ; Wed, 03 Feb 2016 18:42:08 +0000 Received: from mail-pf0-x22d.google.com ([2607:f8b0:400e:c00::22d]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aR2Lc-00081v-18 for linux-arm-kernel@lists.infradead.org; Wed, 03 Feb 2016 18:40:28 +0000 Received: by mail-pf0-x22d.google.com with SMTP id n128so17919970pfn.3 for ; Wed, 03 Feb 2016 10:39:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PraNqYFxepoI8Z3g2lBe6OWiBAOB6daEao/96jQ78Dk=; b=AcZUkX9CSaddNzqoHGxmV5hgeNnC0sJEqUjIeuGIvkOjwEvD9Q0Syx2chFJOaWxh/H ioe3K7L4jRxUgPkBZyef7zKYP+CpY7dcm8ExSQ4iHb/GguAAHqxWbfFxTQ5ImQANHzzH F4YjqjzhXI0rJycszySB2K2p/6+syc9tw8J6Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PraNqYFxepoI8Z3g2lBe6OWiBAOB6daEao/96jQ78Dk=; b=VEr0rlpimlZ2TJFroMBAI58cn9dc1KfDRDG1aUjh+bJb56BTa9MqDnHxrHxZuWRkFp NQFjXCl5DchLOxzr86DUmmm0CQu+lqgfNPmqXQuP1UINu5PrAqmkkU3QruwaxmKQQj3C A/HwcDEiQoe7EkHRqNMH5ViLBKEB2FHpzUeEQsV2ymcHU+EmODXjARMDZCs0VWXrsYUp Zzezot+VwZwDI9LrpqT5R/+XCbIpOoCqgT+fKa1V9iVeLd4zEBpK9gK8kjpNGjw1++3D zuAoe0h/5pzWqiHiXCmgvAzpzWBBCaTzEIJynxuy30snro6/5LGrGjsWOnC54cd2LFJ8 xgYw== X-Gm-Message-State: AG10YOTaJ4Q6UL1s1CZnoBo6HQCi2kSD8ivphtCWXrEPQNzOn9d96FKaPIr+kyrvLCTAuY7T X-Received: by 10.98.43.88 with SMTP id r85mr4478960pfr.7.1454524794118; Wed, 03 Feb 2016 10:39:54 -0800 (PST) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id xa9sm11369704pab.44.2016.02.03.10.39.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 03 Feb 2016 10:39:53 -0800 (PST) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Subject: [PATCH V9 11/18] coresight: etm3x: consolidating initial config Date: Wed, 3 Feb 2016 11:39:09 -0700 Message-Id: <1454524756-10628-12-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1454524756-10628-1-git-send-email-mathieu.poirier@linaro.org> References: <1454524756-10628-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160203_104012_368951_FEE41B1B X-CRM114-Status: GOOD ( 12.14 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2607:f8b0:400e:c00:0:0:0:22d listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alexander.shishkin@linux.intel.com, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, tor@ti.com, mike.leach@arm.com, zhang.chunyan@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org There is really no point in having two functions to take care of doing the initial tracer configuration. As such moving everything to 'etm_set_default()'. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm3x.c | 37 ++++++++++----------------- 1 file changed, 14 insertions(+), 23 deletions(-) -- 2.1.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 92139674bea4..34a69583ccbc 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -41,7 +41,6 @@ module_param_named(boot_enable, boot_enable, int, S_IRUGO); /* The number of ETM/PTM currently registered */ static int etm_count; static struct etm_drvdata *etmdrvdata[NR_CPUS]; -static void etm_init_default_data(struct etm_config *config); /* * Memory mapped writes to clear os lock are not supported on some processors @@ -194,6 +193,19 @@ void etm_set_default(struct etm_config *config) if (WARN_ON_ONCE(!config)) return; + /* + * Taken verbatim from the TRM: + * + * To trace all memory: + * set bit [24] in register 0x009, the ETMTECR1, to 1 + * set all other bits in register 0x009, the ETMTECR1, to 0 + * set all bits in register 0x007, the ETMTECR2, to 0 + * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). + */ + config->enable_ctrl1 = BIT(24); + config->enable_ctrl2 = 0x0; + config->enable_event = ETM_HARD_WIRE_RES_A; + config->trigger_event = ETM_DEFAULT_EVENT_VAL; config->enable_event = ETM_HARD_WIRE_RES_A; @@ -577,27 +589,6 @@ static void etm_init_arch_data(void *info) CS_LOCK(drvdata->base); } -static void etm_init_default_data(struct etm_config *config) -{ - if (WARN_ON_ONCE(!config)) - return; - - etm_set_default(config); - - /* - * Taken verbatim from the TRM: - * - * To trace all memory: - * set bit [24] in register 0x009, the ETMTECR1, to 1 - * set all other bits in register 0x009, the ETMTECR1, to 0 - * set all bits in register 0x007, the ETMTECR2, to 0 - * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). - */ - config->enable_ctrl1 = BIT(24); - config->enable_ctrl2 = 0x0; - config->enable_event = ETM_HARD_WIRE_RES_A; -} - static void etm_init_trace_id(struct etm_drvdata *drvdata) { /* @@ -674,7 +665,7 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) } etm_init_trace_id(drvdata); - etm_init_default_data(&drvdata->config); + etm_set_default(&drvdata->config); desc->type = CORESIGHT_DEV_TYPE_SOURCE; desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;