From patchwork Mon Apr 4 14:52:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 65008 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp1232866lbc; Mon, 4 Apr 2016 07:55:35 -0700 (PDT) X-Received: by 10.98.69.75 with SMTP id s72mr22336738pfa.66.1459781734584; Mon, 04 Apr 2016 07:55:34 -0700 (PDT) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id d5si943395pas.63.2016.04.04.07.55.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Apr 2016 07:55:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1an5tc-00065N-Ag; Mon, 04 Apr 2016 14:54:28 +0000 Received: from mail-lb0-x234.google.com ([2a00:1450:4010:c04::234]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1an5sG-00057C-SC for linux-arm-kernel@lists.infradead.org; Mon, 04 Apr 2016 14:53:07 +0000 Received: by mail-lb0-x234.google.com with SMTP id bc4so163628541lbc.2 for ; Mon, 04 Apr 2016 07:52:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wCRj/BHT8Xdiud8uJen3IzrKxCtwTZnVp0mFOrL/1Lo=; b=K2kdClkgPHcgyzKTd0aP7VoKMyV2+i76NN7FAryWSXa2Geys0XSlRW4RTRUGJr5Uj/ IRTRbaLhzRhq6DPddy/x8lSJbRlQv40uv25n3TGKU6VHEDXN0+fQfGTVoNtK/pRiZKQp /IlUtyLhLfB9qbHhQvT0/YpVkioJBOeBettOw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wCRj/BHT8Xdiud8uJen3IzrKxCtwTZnVp0mFOrL/1Lo=; b=ESBaO9RzNRfNxU9lfZeMr8Ib+RH9i+SoUnN9FeNMk/Cpiubc3s3tLkm0orUp6Pl9jb RQWc7XAnPJhymM+wcx1z0xwOF1+6MZl/deedLBXVJ3j7Vd2pEPNhieNtWFlI/zVoh7Io YhLQJKHhLSbbahrGi9cURcGZ5oMGjbdI3bxAwW67L0lypVD0SrJB1QNvrpTH8QVBWMSt lm9u3UHISOlb42e9S+zVGlODkJ6mPAas8vxTUn66r3hzHKzK20fvaG5/z4kc9BjXXuMu BOYypZ1iEK+BhIpFnlg/i4YCGUXCK7MuU39SJWWsgvbFAE5buaFaL7TS484XAKgdnrsX gijw== X-Gm-Message-State: AD7BkJIIrdejUvp/fQws8yo9+uDii/OArxTSgN+9ZAgWiHlMT7bSKeMMB3lM0kxgV/HvG+lx X-Received: by 10.28.50.133 with SMTP id y127mr12700724wmy.4.1459781561124; Mon, 04 Apr 2016 07:52:41 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id cf6sm7922528wjc.12.2016.04.04.07.52.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 04 Apr 2016 07:52:40 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, will.deacon@arm.com, catalin.marinas@arm.com, mark.rutland@arm.com Subject: [PATCH 6/8] arm64/kernel: pass virtual entry point as __enable_mmu() argument Date: Mon, 4 Apr 2016 16:52:22 +0200 Message-Id: <1459781544-14310-7-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1459781544-14310-1-git-send-email-ard.biesheuvel@linaro.org> References: <1459781544-14310-1-git-send-email-ard.biesheuvel@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160404_075305_319809_F3A670AE X-CRM114-Status: GOOD ( 14.34 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2a00:1450:4010:c04:0:0:0:234 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Instead of keeping the virtual entry point to be invoked by __enable_mmu in a callee saved register with file scope, simply pass it as the second argument. This makes the code easier to maintain. Signed-off-by: Ard Biesheuvel --- arch/arm64/kernel/head.S | 27 ++++++++++---------- 1 file changed, 14 insertions(+), 13 deletions(-) -- 2.5.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 9201cddb53bc..d28fc345bec3 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -222,10 +222,10 @@ ENTRY(stext) * On return, the CPU will be ready for the MMU to be turned on and * the TCR will have been set. */ - ldr x27, 0f // address to jump to after + bl __cpu_setup // initialise processor + ldr x1, 0f // address to jump to after // MMU has been enabled - adr_l lr, __enable_mmu // return (PIC) address - b __cpu_setup // initialise processor + b __enable_mmu ENDPROC(stext) .align 3 0: .quad __mmap_switched - (_head - TEXT_OFFSET) + KIMAGE_VADDR @@ -696,7 +696,7 @@ ENTRY(secondary_startup) */ bl __cpu_setup // initialise processor - ldr x27, .L__secondary_switched + ldr x1, .L__secondary_switched b __enable_mmu ENDPROC(secondary_startup) @@ -741,7 +741,7 @@ ENTRY(__early_cpu_boot_status) * Enable the MMU. * * x0 = SCTLR_EL1 value for turning on the MMU. - * x27 = *virtual* address to jump to upon completion + * x1 = *virtual* address to jump to upon completion * * Other registers depend on the function called upon completion. * @@ -751,11 +751,11 @@ ENTRY(__early_cpu_boot_status) .section ".idmap.text", "ax" __enable_mmu: mrs x22, sctlr_el1 // preserve old SCTLR_EL1 value - mrs x1, ID_AA64MMFR0_EL1 - ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4 - cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED + mrs x2, ID_AA64MMFR0_EL1 + ubfx x3, x2, #ID_AA64MMFR0_TGRAN_SHIFT, 4 + cmp x3, #ID_AA64MMFR0_TGRAN_SUPPORTED b.ne __no_granule_support - update_early_cpu_boot_status 0, x1, x2 + update_early_cpu_boot_status 0, x2, x3 adrp x4, idmap_pg_dir adrp x5, swapper_pg_dir msr ttbr0_el1, x4 // load TTBR0 @@ -771,9 +771,10 @@ __enable_mmu: ic iallu dsb nsh isb + mov x20, x1 // preserve branch target #ifdef CONFIG_RANDOMIZE_BASE mov x19, x0 // preserve new SCTLR_EL1 value - blr x27 + blr x1 /* * If we return here, we have a KASLR displacement in x23 which we need @@ -789,14 +790,14 @@ __enable_mmu: ic iallu // flush instructions fetched dsb nsh // via old mapping isb - add x27, x27, x23 // relocated __mmap_switched + add x20, x20, x23 // relocated __mmap_switched #endif - br x27 + br x20 ENDPROC(__enable_mmu) __no_granule_support: /* Indicate that this CPU can't boot and is stuck in the kernel */ - update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2 + update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x2, x3 1: wfe wfi