From patchwork Wed Nov 23 13:01:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vijay Kilari X-Patchwork-Id: 83662 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp2628442qge; Wed, 23 Nov 2016 05:12:24 -0800 (PST) X-Received: by 10.84.216.92 with SMTP id f28mr6493778plj.31.1479906744737; Wed, 23 Nov 2016 05:12:24 -0800 (PST) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id 2si33758203pfd.204.2016.11.23.05.12.24 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 Nov 2016 05:12:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gmail.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org; dmarc=fail (p=NONE dis=NONE) header.from=gmail.com Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1c9XKY-0005a6-IQ; Wed, 23 Nov 2016 13:11:18 +0000 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1c9XCU-00042G-Eq for linux-arm-kernel@lists.infradead.org; Wed, 23 Nov 2016 13:03:02 +0000 Received: by mail-pg0-x241.google.com with SMTP id p66so1091718pga.2 for ; Wed, 23 Nov 2016 05:02:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pB1m1Yb6SjrLXpmZZlE1IEbORleHLzM6BDbb0OA6RSM=; b=AEsV4GUWEZXjVxTXc3BrCumBgw0KW0ttVRlo2LsQbIVyuITqZIkvBohKn6/ClV1JD5 rRNIl3i85O8bV4AiBseCWVyugGizOoif7/Pjx5aIM90zSWnWaSr8/3rXyPtSjq7NK4Yo yRzYVUAKomeRBbxdf6ZI22k5YX3ajayrGAG1ey/Vvb06Qu4kXRgdro0Aln2iiSnCijQj clPviuRKRLQAycjphvA+rBi7xsInk08O8c0AmZYCBkMT5gyCdb/VruIGn0yneTZow+G5 Mc1VwhqMYAOiG+8ewEyEQM4w7p/K0d2XuN+ZUyBUaubBtZDC8Kd6neqdw8LJkAL2ZAez IncA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pB1m1Yb6SjrLXpmZZlE1IEbORleHLzM6BDbb0OA6RSM=; b=B2VO9065bwB/7P4SHHt8mAmY61BmAtD8xbCKrhiOUQdCDxpasMPDiwQoQRQrvBPlLR 53LRLOpuLenpcLu5F79BOttabq7qNbdpd+uC8CfwOfYhFM1SeQIChVWxCOHOJn0cK+FM WVxmzk7RPDs6Z8jOxkx+kPeELD8ygQ+G2ML1x4/ulzSdA6A+K8kFmtOeu5a3AXQXjEeF 137iZNTlns8m+/sD7cAteD7g5Cce5y1kTADYYXprkkNROildSilSUxfW8MP6kPYghnom evvO/2RMx2Vu0d5fGyzOt3Q0xjJvwdxATsTjw2g3bukRsFUG5rPW3rwZgyPl/rNmDyKG Um4Q== X-Gm-Message-State: AKaTC01eKZUteeyvH+8hJ6cE9ZK1VeC+0zEp2UYKB4hGdPv8QfgKfsfujwuMvyifMgNhHw== X-Received: by 10.98.198.207 with SMTP id x76mr2696298pfk.33.1479906160949; Wed, 23 Nov 2016 05:02:40 -0800 (PST) Received: from cavium-Vostro-2520.caveonetworks.com ([111.93.218.67]) by smtp.gmail.com with ESMTPSA id a24sm36838849pfh.57.2016.11.23.05.02.38 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 23 Nov 2016 05:02:40 -0800 (PST) From: vijay.kilari@gmail.com To: marc.zyngier@arm.com, christoffer.dall@linaro.org, peter.maydell@linaro.org Subject: [PATCH v9 11/11] arm: vgic: Save and restore GICv3 CPU interface regs for AArch32 Date: Wed, 23 Nov 2016 18:31:58 +0530 Message-Id: <1479906118-15832-12-git-send-email-vijay.kilari@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1479906118-15832-1-git-send-email-vijay.kilari@gmail.com> References: <1479906118-15832-1-git-send-email-vijay.kilari@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161123_050258_659520_32D48708 X-CRM114-Status: GOOD ( 15.49 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.8 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [111.93.218.67 listed in dnsbl.sorbs.net] -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [2607:f8b0:400e:c05:0:0:0:241 listed in] [list.dnswl.org] 1.3 RCVD_IN_BL_SPAMCOP_NET RBL: Received via a relay in bl.spamcop.net [Blocked - see ] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (vijay.kilari[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: p.fedin@samsung.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Vijaya Kumar K MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org From: Vijaya Kumar K Use coproc_reg infrastructure to save and restore CPU interface register of GICv3 for AArch32 host. Signed-off-by: Vijaya Kumar K --- arch/arm/kvm/Makefile | 2 + virt/kvm/arm/vgic/vgic-coproc-reg-v3.c | 155 +++++++++++++++++++++++++++++++++ 2 files changed, 157 insertions(+) -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile index d571243..451e666 100644 --- a/arch/arm/kvm/Makefile +++ b/arch/arm/kvm/Makefile @@ -32,6 +32,8 @@ obj-y += $(KVM)/arm/vgic/vgic-mmio.o obj-y += $(KVM)/arm/vgic/vgic-mmio-v2.o obj-y += $(KVM)/arm/vgic/vgic-mmio-v3.o obj-y += $(KVM)/arm/vgic/vgic-kvm-device.o +obj-y += $(KVM)/arm/vgic/vgic-sys-reg-common.o +obj-y += $(KVM)/arm/vgic/vgic-coproc-reg-v3.o obj-y += $(KVM)/arm/vgic/vgic-its.o obj-y += $(KVM)/irqchip.o obj-y += $(KVM)/arm/arch_timer.o diff --git a/virt/kvm/arm/vgic/vgic-coproc-reg-v3.c b/virt/kvm/arm/vgic/vgic-coproc-reg-v3.c new file mode 100644 index 0000000..25d00e5 --- /dev/null +++ b/virt/kvm/arm/vgic/vgic-coproc-reg-v3.c @@ -0,0 +1,155 @@ +/* + * VGIC system registers handling functions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "vgic.h" +#include "coproc.h" + +#define ACCESS_COPROC_REG(REG) \ +static bool access_gic_##REG##_coproc_reg(struct kvm_vcpu *vcpu, \ + struct coproc_params *p, \ + const struct coproc_reg *r) \ +{ \ + return access_gic_##REG##_reg(vcpu, p->is_write, &p->Rt1); \ +} + +ACCESS_COPROC_REG(ctlr) +ACCESS_COPROC_REG(pmr) +ACCESS_COPROC_REG(bpr0) +ACCESS_COPROC_REG(bpr1) +ACCESS_COPROC_REG(sre) +ACCESS_COPROC_REG(grpen0) +ACCESS_COPROC_REG(grpen1) + +#define ACCESS_COPROC_APNR_REG(REG) \ +static bool access_gic_##REG##_coproc_reg(struct kvm_vcpu *vcpu, \ + struct coproc_params *p, \ + const struct coproc_reg *r) \ +{ \ + u8 idx = p->Op2 & 3; \ + \ + return access_gic_##REG##_reg(vcpu, p->is_write, idx, &p->Rt1); \ +} + +ACCESS_COPROC_APNR_REG(ap0r) +ACCESS_COPROC_APNR_REG(ap1r) + +static const struct coproc_reg gic_v3_icc_coproc_reg_descs[] = { + /* ICC_PMR_EL1 */ + { CRn(0), CRm(6), Op1(0), Op2(0), is32, access_gic_pmr_coproc_reg }, + /* ICC_BPR0_EL1 */ + { CRn(12), CRm(8), Op1(0), Op2(3), is32, access_gic_bpr0_coproc_reg }, + /* ICC_AP0R0_EL1 */ + { CRn(12), CRm(8), Op1(0), Op2(4), is32, access_gic_ap0r_coproc_reg }, + /* ICC_AP0R1_EL1 */ + { CRn(12), CRm(8), Op1(0), Op2(5), is32, access_gic_ap0r_coproc_reg }, + /* ICC_AP0R2_EL1 */ + { CRn(12), CRm(8), Op1(0), Op2(6), is32, access_gic_ap0r_coproc_reg }, + /* ICC_AP0R3_EL1 */ + { CRn(12), CRm(8), Op1(0), Op2(7), is32, access_gic_ap0r_coproc_reg }, + /* ICC_AP1R0_EL1 */ + { CRn(12), CRm(9), Op1(0), Op2(0), is32, access_gic_ap1r_coproc_reg }, + /* ICC_AP1R1_EL1 */ + { CRn(12), CRm(9), Op1(0), Op2(1), is32, access_gic_ap1r_coproc_reg }, + /* ICC_AP1R2_EL1 */ + { CRn(12), CRm(9), Op1(0), Op2(2), is32, access_gic_ap1r_coproc_reg }, + /* ICC_AP1R3_EL1 */ + { CRn(12), CRm(9), Op1(0), Op2(3), is32, access_gic_ap1r_coproc_reg }, + /* ICC_BPR1_EL1 */ + { CRn(12), CRm(12), Op1(0), Op2(3), is32, access_gic_bpr1_coproc_reg }, + /* ICC_CTLR_EL1 */ + { CRn(12), CRm(12), Op1(0), Op2(4), is32, access_gic_ctlr_coproc_reg }, + /* ICC_SRE_EL1 */ + { CRn(12), CRm(12), Op1(0), Op2(5), is32, access_gic_sre_coproc_reg }, + /* ICC_IGRPEN0_EL1 */ + { CRn(12), CRm(12), Op1(0), Op2(6), is32, + access_gic_grpen0_coproc_reg }, + /* ICC_GRPEN1_EL1 */ + { CRn(12), CRm(12), Op1(0), Op2(7), is32, + access_gic_grpen1_coproc_reg }, +}; + + +#define KVM_DEV_ARM_VGIC_COPROC_MASK 0x3fff + +/* As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt, + * CPUREGs id is passed in AArch64 system register encoding format. + * Format to COPROC register format for AArch32 mode before using. + */ +static u64 vgic_to_cpreg(u64 id) +{ + u64 cpreg = 0; + + id = id & KVM_DEV_ARM_VGIC_COPROC_MASK; + cpreg = ((id & KVM_REG_ARM_VGIC_SYSREG_OP2_MASK) >> + KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT) << + KVM_REG_ARM_32_OPC2_SHIFT; + cpreg |= ((id & KVM_REG_ARM_VGIC_SYSREG_CRM_MASK) >> + KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT) << KVM_REG_ARM_CRM_SHIFT; + cpreg |= ((id & KVM_REG_ARM_VGIC_SYSREG_CRN_MASK) >> + KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT) << + KVM_REG_ARM_32_CRN_SHIFT; + cpreg |= ((id & KVM_REG_ARM_VGIC_SYSREG_OP1_MASK) >> + KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT) << KVM_REG_ARM_OPC1_SHIFT; + id |= (KVM_REG_ARM_COPROC_MASK | KVM_REG_SIZE_U32); + + return cpreg; +} + +int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id, + u64 *reg) +{ + struct coproc_params params; + u64 cpreg = vgic_to_cpreg(id); + + params.Rt1 = *reg; + params.is_write = is_write; + params.is_64bit = false; + + if (find_coproc_reg_by_id(cpreg, ¶ms, gic_v3_icc_coproc_reg_descs, + ARRAY_SIZE(gic_v3_icc_coproc_reg_descs))) + return 0; + + return -ENOENT; +} + +int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write, u64 id, + u64 *reg) +{ + struct coproc_params params; + const struct coproc_reg *r; + u64 cpreg = vgic_to_cpreg(id); + + if (is_write) + params.Rt1 = *reg; + params.is_write = is_write; + params.is_64bit = false; + + r = find_coproc_reg_by_id(cpreg, ¶ms, gic_v3_icc_coproc_reg_descs, + ARRAY_SIZE(gic_v3_icc_coproc_reg_descs)); + if (!r) + return -ENXIO; + + if (!r->access(vcpu, ¶ms, r)) + return -EINVAL; + + if (!is_write) + *reg = params.Rt1; + + return 0; +}