From patchwork Thu Aug 25 14:46:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 101934 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp880718qga; Thu, 25 Aug 2016 07:48:52 -0700 (PDT) X-Received: by 10.107.14.4 with SMTP id 4mr10653649ioo.160.1472136532853; Thu, 25 Aug 2016 07:48:52 -0700 (PDT) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id c4si15862243pfb.9.2016.08.25.07.48.52 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Aug 2016 07:48:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bcvwg-0004TJ-SS; Thu, 25 Aug 2016 14:47:54 +0000 Received: from mout.kundenserver.de ([212.227.17.13]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bcvwJ-00048F-AN for linux-arm-kernel@lists.infradead.org; Thu, 25 Aug 2016 14:47:34 +0000 Received: from wuerfel.lan. ([78.42.132.4]) by mrelayeu.kundenserver.de (mreue102) with ESMTPA (Nemesis) id 0Mg7K1-1boq8k15Px-00NPD4; Thu, 25 Aug 2016 16:46:51 +0200 From: Arnd Bergmann To: Russell King Subject: [PATCH 2/2] smc91x: remove ARM hack for unaligned 16-bit writes Date: Thu, 25 Aug 2016 16:46:21 +0200 Message-Id: <20160825144633.1850889-2-arnd@arndb.de> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20160825144633.1850889-1-arnd@arndb.de> References: <20160825144633.1850889-1-arnd@arndb.de> X-Provags-ID: V03:K0:pSakRnSaRm6vbeHi73qPahTVNpDT6NvAs/ONcA4o4FXlJrkI3ex CUL1EFDDK2337PgzrjQwG3nexWI8b1IgIdn2r5rKGYPMKHRuPxjVn6OcUwULhQg5eDZqRir 9Vkip7ehLU6QJIgUKqTEDhJCeVtYAiAHwsmPTm9Bx6HAwYRSvjt/TWRrV9lkbjJoKmmUFkZ vGS5jeYsEos/LDhAZQB6g== X-UI-Out-Filterresults: notjunk:1; V01:K0:iT+rMLQG54E=:7K13SOi8icpjRs9afHgpQS jcP/G54GSoIQ6yQpLfWvxeeQHNSGSM5bDfgWLuHfDir0ZeYDMFQo+QdP7UH7YslWYPndtggla bb7sEuc5k/9zl70hXEy//ar2jWUebhXcmyJ8DX14Nl/3R9QG0oMvH2CZpXp0LGgVijZjhZEjR TtyPKAKuoChb8QHeesaEy+NWNhNXM+meMNMH1iAfWk/WNxwg5MEtyZofA08zYFw63Cb6ovvqr BwUeenC4zB2Appaeboxy0MRknbrzqEAp5ESlxQJIIQjqR5x/XzzwCEkqf3OP/MFP5/vY/GQQY pnmyH1K3v0sCj3RoG2N2P7XYPn9z5G6LAMnoh1jHZfM2iDBXlL8E+wjACb/LuGF4jI2VbzFXG i/pQlEem32RmJ0bkbGiSmvgHXC8/Xfah+7asVGNchDq7hZwT+uwRFxqvn3XmI1UGWMv7GCEIE uZ9VHn/tN5hrGTMSwJCBxoUaO98dW3cDQegx0QohfEypbA76nvAcpYr/lnl/spp2dv7LgylVd zhYf9lGBv/ktY7CaVBJxb8Mhn3pk6MfGxF2tVGlZW6CQVghuJ+B2ooNAU04AJ1Qd11wENojBS tbUel8naMEbMt7yiP3of3sLHsOjmdNepQYEP3M4K/sZcYZHrhWuwy6vhjx3Jxo50ULzasmMQo m7Jcp92GDblTw3Q26t+sCl/YKicbOTcSMT4Te9veabr1VH8WZLCqNbRudXVG19zM5xtU= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160825_074731_800312_7288E738 X-CRM114-Status: GOOD ( 19.08 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [212.227.17.13 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [212.227.17.13 listed in wl.mailspike.net] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Arnd Bergmann , Yoshinori Sato , Nicolas Pitre , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Robert Jarzmik , "David S. Miller" , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org The ARM specific I/O operations are almost the same as the generic ones, with the exception of the SMC_outw macro that works around a problem of some platforms that cannot write to 16-bit registers at an address that is not 32-bit aligned. By inspection, I found that this is handled already in the register abstractions for almost all cases, the exceptions being SMC_SET_MAC_ADDR() and SMC_SET_MCAST(). I assume that all platforms that require the hack for the other registers also need it here, so the ones listed explictly here are the only ones that work correctly, while the other ones either don't need the hack at all, or they will set an incorrect MAC address (which can often go unnoticed). This changes the two macros that set the unaligned registers to use 32-bit writes if possible, which should do the right thing in all combinations. The ARM specific SMC_outw gets removed as a consequence. The only difference between the ARM behavior and the default is the selection of the LED settings. The fact that we have different defaults based on the CPU architectures here is a bit suspicious, but probably harmless, and I have no plan of touching that. Signed-off-by: Arnd Bergmann --- drivers/net/ethernet/smsc/smc91x.h | 50 +++++++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 20 deletions(-) -- 2.9.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/drivers/net/ethernet/smsc/smc91x.h b/drivers/net/ethernet/smsc/smc91x.h index 22333477d0b5..908473d9ede0 100644 --- a/drivers/net/ethernet/smsc/smc91x.h +++ b/drivers/net/ethernet/smsc/smc91x.h @@ -58,6 +58,7 @@ #define SMC_inw(a, r) readw((a) + (r)) #define SMC_inl(a, r) readl((a) + (r)) #define SMC_outb(v, a, r) writeb(v, (a) + (r)) +#define SMC_outw(v, a, r) writew(v, (a) + (r)) #define SMC_outl(v, a, r) writel(v, (a) + (r)) #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) @@ -65,19 +66,6 @@ #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) #define SMC_IRQ_FLAGS (-1) /* from resource */ -/* We actually can't write halfwords properly if not word aligned */ -static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg) -{ - if ((machine_is_mainstone() || machine_is_stargate2() || - machine_is_pxa_idp()) && reg & 2) { - unsigned int v = val << 16; - v |= readl(ioaddr + (reg & ~2)) & 0xffff; - writel(v, ioaddr + (reg & ~2)); - } else { - writew(val, ioaddr + reg); - } -} - #elif defined(CONFIG_SH_SH4202_MICRODEV) #define SMC_CAN_USE_8BIT 0 @@ -1029,18 +1017,40 @@ static const char * chip_ids[ 16 ] = { #define SMC_SET_MAC_ADDR(lp, addr) \ do { \ - SMC_out16(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \ - SMC_out16(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \ - SMC_out16(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \ + if (SMC_32BIT(lp)) { \ + SMC_outl((addr[0] )|(addr[1] << 8) | \ + (addr[2] << 16)|(addr[3] << 24), \ + ioaddr, ADDR0_REG(lp)); \ + } else { \ + SMC_out16(addr[0]|(addr[1] << 8), ioaddr, \ + ADDR0_REG(lp)); \ + SMC_out16(addr[2]|(addr[3] << 8), ioaddr, \ + ADDR1_REG(lp)); \ + } \ + SMC_out16(addr[4]|(addr[5] << 8), ioaddr, \ + ADDR2_REG(lp)); \ } while (0) #define SMC_SET_MCAST(lp, x) \ do { \ const unsigned char *mt = (x); \ - SMC_out16(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \ - SMC_out16(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \ - SMC_out16(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \ - SMC_out16(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \ + if (SMC_32BIT(lp)) { \ + SMC_outl((mt[0] ) | (mt[1] << 8) | \ + (mt[2] << 16) | (mt[3] << 24), \ + ioaddr, MCAST_REG1(lp)); \ + SMC_outl((mt[4] ) | (mt[5] << 8) | \ + (mt[6] << 16) | (mt[7] << 24), \ + ioaddr, MCAST_REG3(lp)); \ + } else { \ + SMC_out16(mt[0] | (mt[1] << 8), \ + ioaddr, MCAST_REG1(lp)); \ + SMC_out16(mt[2] | (mt[3] << 8), \ + ioaddr, MCAST_REG2(lp)); \ + SMC_out16(mt[4] | (mt[5] << 8), \ + ioaddr, MCAST_REG3(lp)); \ + SMC_out16(mt[6] | (mt[7] << 8), \ + ioaddr, MCAST_REG4(lp)); \ + } \ } while (0) #define SMC_PUT_PKT_HDR(lp, status, length) \