From patchwork Thu May 8 00:15:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 29816 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ie0-f199.google.com (mail-ie0-f199.google.com [209.85.223.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id A029520534 for ; Thu, 8 May 2014 00:18:01 +0000 (UTC) Received: by mail-ie0-f199.google.com with SMTP id rl12sf8573201iec.2 for ; Wed, 07 May 2014 17:18:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:message-id:date:from:user-agent :mime-version:to:subject:references:in-reply-to:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :sender:errors-to:x-original-sender :x-original-authentication-results:mailing-list:content-type :content-transfer-encoding; bh=Q2DBDjlvabTmZ0r9jb6k+PJczpe6U8iCWrXjQcCp1l8=; b=B6bY6F6NGA6NFEsx1J6kZjdIbHMs/FhE7vFxMJQkS+MV/QX6Lrcz6NVDtEinYcKnHX Q9ImXWlA+aQO06GykFduJrxRjSgFR2vB0SdBZITUGC37EfQ6FUyGddwbrmiPOppdZkxE vLEMgjFWK+nLyRHZVPoWEcA3ruC84xANEckaSXaTF2gmfY8rGGUcPCvDwj/+JZgveQmq GX67Fags3ggS0dE9wFhwB4RJfdxhyE/6A6fLt8zix4QfMJO4SQ0SZsqOUigGt7CdZlAP LG8LliI3LB8Xb1BkD86JofbY7BnDH50gl3HyyOzQqFhFll7/Q5NdkivAhT3y4tACGNwr UHTQ== X-Gm-Message-State: ALoCoQneELk7iL5PBFubPpP6JUsk7haySzTy7YGaA6TpQRDNvFcEzJ2x2t5Th962l0kgvwm4SGZK X-Received: by 10.182.104.70 with SMTP id gc6mr127964obb.35.1399508280691; Wed, 07 May 2014 17:18:00 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.41.8 with SMTP id y8ls1154685qgy.11.gmail; Wed, 07 May 2014 17:18:00 -0700 (PDT) X-Received: by 10.58.160.134 with SMTP id xk6mr144373veb.64.1399508280552; Wed, 07 May 2014 17:18:00 -0700 (PDT) Received: from mail-vc0-f174.google.com (mail-vc0-f174.google.com [209.85.220.174]) by mx.google.com with ESMTPS id de9si3185183vcb.105.2014.05.07.17.18.00 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 07 May 2014 17:18:00 -0700 (PDT) Received-SPF: none (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) client-ip=209.85.220.174; Received: by mail-vc0-f174.google.com with SMTP id ib6so2341608vcb.33 for ; Wed, 07 May 2014 17:18:00 -0700 (PDT) X-Received: by 10.52.116.101 with SMTP id jv5mr104446vdb.11.1399508280423; Wed, 07 May 2014 17:18:00 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp352306vcb; Wed, 7 May 2014 17:18:00 -0700 (PDT) X-Received: by 10.140.42.85 with SMTP id b79mr208315qga.87.1399508279834; Wed, 07 May 2014 17:17:59 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id d5si7580419qad.155.2014.05.07.17.17.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 May 2014 17:17:59 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WiBzw-0001C5-T7; Thu, 08 May 2014 00:15:40 +0000 Received: from mail-ie0-f175.google.com ([209.85.223.175]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WiBzt-0001BF-6Q for linux-arm-kernel@lists.infradead.org; Thu, 08 May 2014 00:15:38 +0000 Received: by mail-ie0-f175.google.com with SMTP id rl12so1846584iec.34 for ; Wed, 07 May 2014 17:15:15 -0700 (PDT) X-Received: by 10.50.153.72 with SMTP id ve8mr49302018igb.16.1399508115331; Wed, 07 May 2014 17:15:15 -0700 (PDT) Received: from [172.22.22.4] (c-71-195-31-37.hsd1.mn.comcast.net. [71.195.31.37]) by mx.google.com with ESMTPSA id hi8sm1358002igb.8.2014.05.07.17.15.14 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 07 May 2014 17:15:14 -0700 (PDT) Message-ID: <536ACC97.3090102@linaro.org> Date: Wed, 07 May 2014 19:15:19 -0500 From: Alex Elder User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 To: "linux-arm-kernel@lists.infradead.org" Subject: Fwd: [PATCH] devicetree: bindings: separate CPU enable method descriptions References: <1399505033-3368-1-git-send-email-elder@linaro.org> In-Reply-To: <1399505033-3368-1-git-send-email-elder@linaro.org> X-Enigmail-Version: 1.5.2 X-Forwarded-Message-Id: <1399505033-3368-1-git-send-email-elder@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140507_171537_376327_9012B613 X-CRM114-Status: GOOD ( 19.12 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.2 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.223.175 listed in list.dnswl.org] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: elder@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 I neglected to copy linux-arm-kernel. -Alex -------- Original Message -------- Subject: [PATCH] devicetree: bindings: separate CPU enable method descriptions Date: Wed, 7 May 2014 18:23:53 -0500 From: Alex Elder To: devicetree@vger.kernel.org CC: mark.rutland@arm.com, sboyd@codeaurora.org, rvaswani@codeaurora.org, linux-kernel@vger.kernel.org The bindings for CPU enable methods are defined in ".../arm/cpus.txt". As additional 32-bit ARM CPUS are converted to use the "enable-method" CPU property to imply a particular set of SMP operations to use, the list of these methods is likely to become unwieldy. The current documentation already contains several property descriptions that are meaningful only for certain enable methods. This patch defines a new Documentation subdirectory whose purpose is to give each CPU enable method its own place to define how and when it's used, as well as what other properties (optional or required) are associated with the method. The existing enable method documentation is expanded and moved from ".../arm/cpus.txt" into new files accordingly. Signed-off-by: Alex Elder --- This series is available here: http://git.linaro.org/landing-teams/working/broadcom/kernel.git Branch review/enable-method-bindings .../bindings/arm/cpu-enable-method/README | 20 +++++ .../bindings/arm/cpu-enable-method/arm,psci.txt | 69 ++++++++++++++++ .../arm/cpu-enable-method/qcom,gcc-msm8660 | 30 +++++++ .../arm/cpu-enable-method/qcom,kpss-acc-v1 | 56 +++++++++++++ .../arm/cpu-enable-method/qcom,kpss-acc-v2 | 56 +++++++++++++ .../bindings/arm/cpu-enable-method/spin-table.txt | 96 ++++++++++++++++++++++ Documentation/devicetree/bindings/arm/cpus.txt | 29 +------ 7 files changed, 330 insertions(+), 26 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/README create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/arm,psci.txt create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/qcom,gcc-msm8660 create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/qcom,kpss-acc-v1 create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/qcom,kpss-acc-v2 create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/spin-table.txt @@ -403,5 +381,4 @@ cpus { }; -- -[1] arm/msm/qcom,saw2.txt -[2] arm/msm/qcom,kpss-acc.txt +[1] arm/cpu-enable-method/ diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/README b/Documentation/devicetree/bindings/arm/cpu-enable-method/README new file mode 100644 index 0000000..cc9431e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/README @@ -0,0 +1,20 @@ +========================== +CPU enable-method bindings +========================== + +The device tree describes the layout of CPUs in a machine in a single "cpus" +node, which in turn contains a number of "cpu" sub-nodes defining properties +for each cpu. + +For multiprocessing configurations, CPU cores can be individually enabled +and disabled. The enabling capability is used for SMP startup as well as +CPU hotplug. A CPU enable method--normally specified in the device tree +using an "enable-method" property--defines how cores are enabled. If all +CPUs in a machine use the same enable method and related property values, +these properties should be defined in the "cpus" node, which associates the +property values with all CPUs. Alternatively, every "cpu" node can define +its "enable-method" separately. + +Documents in this directory define how each of the CPU enable methods are to +be used, as well the names and possible values of related properties that +are required by or affect each enable method. diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/arm,psci.txt b/Documentation/devicetree/bindings/arm/cpu-enable-method/arm,psci.txt new file mode 100644 index 0000000..c80d68e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/arm,psci.txt @@ -0,0 +1,69 @@ +==================================== +CPU enable-method "arm,psci" binding +==================================== + +This document describes the "arm,psci" method for enabling secondary CPUs. +This is different from other CPU enable methods, in that CPU cores are +enabled and disabled using the ARM PSCI interface, which is defined in the +device tree independent of the CPUs. Instead, a separate node compatible +with "arm,psci" defines the PSCI functions supported; if a "cpu_on" function +is defined, that is used for enabling a CPU core. + +Enable method: Distinct node with compatible = "arm,psci" property +Compatible cpus: (???) (both 32- and 64-bit ARM have a hook) +Properties: + - method + Usage: required + Value type: + Definition: + A string defining the specific instruction + used to enable the core. The value must be + either "hvc" or "smc". + - cpu_suspend + Usage: optional + Value type: + Definition: + If present, this value defines the PSCI function id + used to suspend execution on a CPU core. + - cpu_off + Usage: optional + Value type: + Definition: + If present, this value defines the PSCI function id + used to power down a CPU core. + - cpu_on + Usage: optional + Value type: + Definition: + If present, this value defines the PSCI function id + used to power up a CPU core. + - migrate + Usage: optional + Value type: + Definition: + If present, this value defines the PSCI function id + used to migrate context to a different CPU core. + +Example (contrived 2-core ARM Cortex-A57 64-bit system): + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_on = 0x1; + }; + cpus { + #size-cells = <0>; + #address-cells = <2>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; /* ??? */ + reg = <0x0 0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x1>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/qcom,gcc-msm8660 b/Documentation/devicetree/bindings/arm/cpu-enable-method/qcom,gcc-msm8660 new file mode 100644 index 0000000..1e002d9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/qcom,gcc-msm8660 @@ -0,0 +1,30 @@ +====================================================== +Secondary CPU enable-method "qcom,gcc-msm8660" binding +====================================================== + +This document describes the "qcom,gcc-msm8660" method for enabling +secondary CPUs. A "qcom,gcc-msm8660" enable method should only be +used in the "cpus" node, to apply to all CPUs. + +Enable method name: "qcom,gcc-msm8660" +Compatible cpu: "qcom,scorpion" +Related properties: (none) + +Example: + + cpus { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,scorpion"; + enable-method = "qcom,gcc-msm8660"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/qcom,kpss-acc-v1 b/Documentation/devicetree/bindings/arm/cpu-enable-method/qcom,kpss-acc-v1 new file mode 100644 index 0000000..3f6ce56 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/qcom,kpss-acc-v1 @@ -0,0 +1,56 @@ +====================================================== +Secondary CPU enable-method "qcom,kpss-acc-v1" binding +====================================================== + +This document describes the "qcom,kpss-acc-v1" method for enabling CPUs. +This enable method can be used in either the "cpus" node or in individual +"cpu" nodes. Note that each "cpu" node must have both "qcom,saw" and +"qcom,acc" properties defined (even if the "enable-method" property was +defined only in the "cpus" node). + +Enable method name: "qcom,kpss-acc-v1" +Compatible machine: "qcom,msm8960" +Compatible cpu: "qcom,krait" +Related properties: + - qcom,saw + Usage: required (in each "cpu" node") + Value type: + Definition: + Specifies the SAW[1] node associated with this CPU. + + - qcom,acc + Usage: required (in each "cpu" node") + Value type: + Definition: + Specifies the ACC[2] node associated with this CPU. + +Example: + +/ { + compatible = "qcom,msm8960"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + }; +}; + +-- +[1] arm/msm/qcom,saw2.txt +[2] arm/msm/qcom,kpss-acc.txt diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/qcom,kpss-acc-v2 b/Documentation/devicetree/bindings/arm/cpu-enable-method/qcom,kpss-acc-v2 new file mode 100644 index 0000000..4368d904 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/qcom,kpss-acc-v2 @@ -0,0 +1,56 @@ +====================================================== +Secondary CPU enable-method "qcom,kpss-acc-v2" binding +====================================================== + +This document describes the "qcom,kpss-acc-v2" method for enabling CPUs. +This enable method can be used in either the "cpus" node or in individual +"cpu" nodes. Note that each "cpu" node must have both "qcom,saw" and +"qcom,acc" properties defined (even if the "enable-method" property was +defined only in the "cpus" node). + +Enable method name: "qcom,kpss-acc-v2" +Compatible machine: "qcom,msm8974" +Compatible cpu: "qcom,krait" +Related properties: + - qcom,saw + Usage: required (in each "cpu" node") + Value type: + Definition: + Specifies the SAW[1] node associated with this CPU. + + - qcom,acc + Usage: required (in each "cpu" node") + Value type: + Definition: + Specifies the ACC[2] node associated with this CPU. + +Example: + +/ { + compatible = "qcom,msm8974"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + }; +}; + +-- +[1] arm/msm/qcom,saw2.txt +[2] arm/msm/qcom,kpss-acc.txt diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/spin-table.txt b/Documentation/devicetree/bindings/arm/cpu-enable-method/spin-table.txt new file mode 100644 index 0000000..f57955a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/spin-table.txt @@ -0,0 +1,96 @@ +================================================ +Secondary CPU enable-method "spin-table" binding +================================================ + +This document describes the "spin-table" method for enabling secondary CPUs. +See the "README" file in this directory for more information on CPU enable +methods. A "spin-table" enable method can be used in either the "cpus" node +or in individual "cpu" nodes. + +Enable method name: "spin-table" +Compatible cpus: "arm,cortex-a57" (?) +Related properties: + - cpu-release-addr + Usage: required + Value type: + Definition: + A two cell value identifying a 64-bit memory location + used by the boot CPU to inform a secondary CPU it + should begin its kernel bootstrap. Memory at this + location must initially be zeroed. + +Examples (contrived 4-core ARM Cortex-A57 64-bit systems): + +The first example uses the same enable method for all cores. + + cpus { + #size-cells = <0>; + #address-cells = <2>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x1>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x100>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x101>; + }; + }; + + +The second example uses specifies distinct enable method properties for each +CPU core. + + cpus { + #size-cells = <0>; + #address-cells = <2>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000008>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000010>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0x20000018>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 333f4ae..2bb2a3e 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -185,30 +185,8 @@ nodes to be present and contain the properties described below. "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" - - - cpu-release-addr - Usage: required for systems that have an "enable-method" - property value of "spin-table". - Value type: - Definition: - # On ARM v8 64-bit systems must be a two cell - property identifying a 64-bit zero-initialised - memory location. - - - qcom,saw - Usage: required for systems that have an "enable-method" - property value of "qcom,kpss-acc-v1" or - "qcom,kpss-acc-v2" - Value type: - Definition: Specifies the SAW[1] node associated with this CPU. - - - qcom,acc - Usage: required for systems that have an "enable-method" - property value of "qcom,kpss-acc-v1" or - "qcom,kpss-acc-v2" - Value type: - Definition: Specifies the ACC[2] node associated with this CPU. - + Details about use of these CPU enable methods is documented + elsewhere[1]. Example 1 (dual-cluster big.LITTLE system 32-bit):