| Message ID | 20210127070811.152690-1-vkoul@kernel.org |
|---|---|
| Headers | show |
| Series | Add clock drivers for SM8350 | expand |
Quoting Vinod Koul (2021-01-26 23:08:09) > From: Vivek Aknurwar <viveka@codeaurora.org> > > Lucid 5LPE is a slightly different Lucid PLL with different offsets and > porgramming sequence so add support for these > > Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org> > Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org> > [vkoul: rebase and tidy up for upstream] > Signed-off-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- Applied to clk-next
Quoting Vinod Koul (2021-01-26 23:08:11) > From: Vivek Aknurwar <viveka@codeaurora.org> > > This adds Global Clock controller (GCC) driver for SM8350 SoC > > Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org> > Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org> > [vkoul: rebase and tidy up for upstream] > Signed-off-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- Applied to clk-next
Quoting Vinod Koul (2021-01-26 23:08:07) > Driver uses regval variable for holding register values, replace with a > shorter one val > > Suggested-by: Stephen Boyd <sboyd@kernel.org> > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Signed-off-by: Vinod Koul <vkoul@kernel.org> > --- Applied to clk-next
This adds gcc clock controller drivers for the controller found in SM8350 SoC Changes in v5: - Add r-b from AngeloGioacchino and Bjorn - Removed unused clock indices - Initialize variable before use in regmap read Changes in v4: - Add Ack from Rob on binding - modularize alpha_pll_trion_set_rate() Changes in v3: - Drop rpmh clk patches applied - Add a new patch to replace regval with val as suggested by Stephen - Fix comments for new Lucid 5LPE PLL: sort new defines by BIT numbers, fix comments, use alpha_pll_check_rate_margin(), rework clk_lucid_5lpe_pll_postdiv_set_rate() logic - Add power domains and optional clocks in bindings - Fix comments for gcc sm8350 driver: clean includes used, use only .fw_name for clocks defined in DT, use floor ops for sdcc clocks, remove critical clocks and enable them in probe, add comments for clks using BRANCH_HALT_SKIP and BRANCH_HALT_DELAY Changes in v2: - Add r-b from Bjorn - Add the gcc_qupv3_wrap_1_{m|s}_ahb_clk and gcc_qupv3_wrap1_s5_clk Vinod Koul (3): clk: qcom: clk-alpha-pll: replace regval with val clk: qcom: clk-alpha-pll: modularize alpha_pll_trion_set_rate() dt-bindings: clock: Add SM8350 GCC clock bindings Vivek Aknurwar (2): clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLL clk: qcom: gcc: Add clock driver for SM8350 .../bindings/clock/qcom,gcc-sm8350.yaml | 96 + drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-alpha-pll.c | 209 +- drivers/clk/qcom/clk-alpha-pll.h | 4 + drivers/clk/qcom/gcc-sm8350.c | 3790 +++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sm8350.h | 254 ++ 7 files changed, 4346 insertions(+), 16 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml create mode 100644 drivers/clk/qcom/gcc-sm8350.c create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8350.h