| Message ID | 20220413231736.991368-1-bryan.odonoghue@linaro.org |
|---|---|
| Headers | show |
| Series | Add camss to SM8250 dtsi | expand |
Hi Bryan, On 4/14/22 02:17, Bryan O'Donoghue wrote: > sm8250 has two CCI busses with two I2C busses apiece. > > Co-developed-by: Julian Grahsl <jgrahsl@snap.com> > Signed-off-by: Julian Grahsl <jgrahsl@snap.com> > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8250.dtsi | 162 +++++++++++++++++++++++++++ > 1 file changed, 162 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index c69a8a88657a..a05ad923bcab 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -3150,6 +3150,88 @@ videocc: clock-controller@abf0000 { > #power-domain-cells = <1>; > }; > > + cci0: cci@ac4f000 { > + compatible = "qcom,sm8250-cci"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + reg = <0 0x0ac4f000 0 0x1000>; > + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; > + power-domains = <&camcc TITAN_TOP_GDSC>; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, > + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CCI_0_CLK>, > + <&camcc CAM_CC_CCI_0_CLK_SRC>; > + clock-names = "camnoc_axi", > + "slow_ahb_src", > + "cpas_ahb", > + "cci", > + "cci_src"; > + > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <&cci0_default>; > + pinctrl-1 = <&cci0_sleep>; > + like as anywhere else it might be better to place 'pinctrl-names' after the 'pinctrl-*' properties. > + status = "disabled"; > + > + cci0_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci0_i2c1: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + cci1: cci@ac50000 { > + compatible = "qcom,sm8250-cci"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + reg = <0 0x0ac50000 0 0x1000>; > + interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; > + power-domains = <&camcc TITAN_TOP_GDSC>; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, > + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CCI_1_CLK>, > + <&camcc CAM_CC_CCI_1_CLK_SRC>; > + clock-names = "camnoc_axi", > + "slow_ahb_src", > + "cpas_ahb", > + "cci", > + "cci_src"; > + > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <&cci1_default>; > + pinctrl-1 = <&cci1_sleep>; > + > + status = "disabled"; > + > + cci1_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci1_i2c1: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > camss: camss@ac6a000 { > compatible = "qcom,sm8250-camss"; > status = "disabled"; > @@ -3687,6 +3769,86 @@ tlmm: pinctrl@f100000 { > gpio-ranges = <&tlmm 0 0 181>; > wakeup-parent = <&pdc>; > > + cci0_default: cci0-default { > + cci0_i2c0_default: cci0-i2c0-default { > + /* SDA, SCL */ > + pins = "gpio101", "gpio102"; > + function = "cci_i2c"; > + > + bias-pull-up; > + drive-strength = <2>; /* 2 mA */ > + }; > + > + cci0_i2c1_default: cci0-i2c1-default { > + /* SDA, SCL */ > + pins = "gpio103", "gpio104"; > + function = "cci_i2c"; > + > + bias-pull-up; > + drive-strength = <2>; /* 2 mA */ > + }; > + }; > + > + cci0_sleep: cci0-sleep { > + cci0_i2c0_sleep: cci0-i2c0-sleep { > + /* SDA, SCL */ > + pins = "gpio101", "gpio102"; > + function = "cci_i2c"; > + > + drive-strength = <2>; /* 2 mA */ > + bias-pull-down; > + }; > + > + cci0_i2c1_sleep: cci0-i2c1-sleep { > + /* SDA, SCL */ > + pins = "gpio103", "gpio104"; > + function = "cci_i2c"; > + > + drive-strength = <2>; /* 2 mA */ > + bias-pull-down; > + }; > + }; > + > + cci1_default: cci1-default { > + cci1_i2c0_default: cci1-i2c0-default { > + /* SDA, SCL */ > + pins = "gpio105","gpio106"; > + function = "cci_i2c"; > + > + bias-pull-up; > + drive-strength = <2>; /* 2 mA */ > + }; > + > + cci1_i2c1_default: cci1-i2c1-default { > + /* SDA, SCL */ > + pins = "gpio107","gpio108"; > + function = "cci_i2c"; > + > + bias-pull-up; > + drive-strength = <2>; /* 2 mA */ > + }; > + }; > + > + cci1_sleep: cci1-sleep { > + cci1_i2c0_sleep: cci1-i2c0-sleep { > + /* SDA, SCL */ > + pins = "gpio105","gpio106"; > + function = "cci_i2c"; > + > + bias-pull-down; > + drive-strength = <2>; /* 2 mA */ > + }; > + > + cci1_i2c1_sleep: cci1-i2c1-sleep { > + /* SDA, SCL */ > + pins = "gpio107","gpio108"; > + function = "cci_i2c"; > + > + bias-pull-down; > + drive-strength = <2>; /* 2 mA */ > + }; > + }; > + > pri_mi2s_active: pri-mi2s-active { > sclk { > pins = "gpio138"; Please feel free to add my Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> -- Best wishes, Vladimir
On 14/04/2022 08:45, Vladimir Zapolskiy wrote: > Hi Bryan, > > On 4/14/22 02:17, Bryan O'Donoghue wrote: >> Adds a CAMSS definition block. >> >> Co-developed-by: Julian Grahsl <jgrahsl@snap.com> >> Signed-off-by: Julian Grahsl <jgrahsl@snap.com> >> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/sm8250.dtsi | 153 +++++++++++++++++++++++++++ >> 1 file changed, 153 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi >> b/arch/arm64/boot/dts/qcom/sm8250.dtsi >> index 906bc8ed25b7..c69a8a88657a 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi >> @@ -3150,6 +3150,159 @@ videocc: clock-controller@abf0000 { >> #power-domain-cells = <1>; >> }; >> + camss: camss@ac6a000 { >> + compatible = "qcom,sm8250-camss"; >> + status = "disabled"; >> + >> + reg = <0 0xac6a000 0 0x2000>, >> + <0 0xac6c000 0 0x2000>, >> + <0 0xac6e000 0 0x1000>, >> + <0 0xac70000 0 0x1000>, >> + <0 0xac72000 0 0x1000>, >> + <0 0xac74000 0 0x1000>, >> + <0 0xacb4000 0 0xd000>, >> + <0 0xacc3000 0 0xd000>, >> + <0 0xacd9000 0 0x2200>, >> + <0 0xacdb200 0 0x2200>; >> + reg-names = "csiphy0", >> + "csiphy1", >> + "csiphy2", >> + "csiphy3", >> + "csiphy4", >> + "csiphy5", >> + "vfe0", >> + "vfe1", >> + "vfe_lite0", >> + "vfe_lite1"; >> + >> + interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "csiphy0", >> + "csiphy1", >> + "csiphy2", >> + "csiphy3", >> + "csiphy4", >> + "csiphy5", >> + "csid0", >> + "csid1", >> + "csid2", >> + "csid3", >> + "vfe0", >> + "vfe1", >> + "vfe_lite0", >> + "vfe_lite1"; >> + >> + power-domains = <&camcc IFE_0_GDSC>, >> + <&camcc IFE_1_GDSC>, >> + <&camcc TITAN_TOP_GDSC>; >> + > > do you need to add 'power-domain-names' property here as well? I looked at this, I don't believe camss depends on it, sdm845 since it does dev_pm_domain_attach_by_id() instead of dev_pm_domain_attach_by_name() > >> + interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc >> SLAVE_CAMERA_CFG>, >> + <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, >> + <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, >> + <&mmss_noc MASTER_CAMNOC_ICP &mc_virt >> SLAVE_EBI_CH0>; > > Recently there was a discussion on the list that interconnects are 2-cells, > if so, the array above should be updated accordingly. Hmm. The above NOC nodes are declared <1> for me, I'll look into this some more though.
V2: - Change 0xHEX to 0xhex - Bjorn - Merge CCI and CCI pin definitions into one patch - Bjorn - Future pinctrl dropped, moved into dts file for board which appears more consistent with sdm845-db845 &tlmm{} section - Bjorn, Bryan - Renamed cci0_i2c0/cci0_i2c1 and cci1_ic20/cci1_i2c1 - Bjorn - Grouped CCI pins into cci0_default, cci0_sleep, etc - Bryan V1: Add in necessary CAMSS, pin and CCI definitions to the SM8250 dtsi. This is the SoC specific stuff, the platform enablement will be done in a separate drop later. On the RB5 platform we have validated ~ 30 FPS @ 4K using the SRGGB10P pixel format provided by a Sony IMX577 sensor. Link: https://git.linaro.org/people/bryan.odonoghue/kernel.git/log/?h=br-v5.19b%2brb5-dts%2bsensors Bryan O'Donoghue (3): arm64: dts: qcom: sm8250: Add camcc DT node arm64: dts: qcom: sm8250: camss: Add CAMSS block definition arm64: dts: qcom: sm8250: camss: Add CCI definitions arch/arm64/boot/dts/qcom/sm8250.dtsi | 330 +++++++++++++++++++++++++++ 1 file changed, 330 insertions(+)