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[0/9] clk: qcom: Add support for SM8550

Message ID 20221116104716.2583320-1-abel.vesa@linaro.org
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Series clk: qcom: Add support for SM8550 | expand

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Abel Vesa Nov. 16, 2022, 10:47 a.m. UTC 
This patchset adds clock support for the Qualcomm SM8550 SoC,
It adds support for the new type of PLL, the TCSR clock controller
driver, support for configurable poll timeout, the RPMh clocks
and the bindings.

To: Andy Gross <agross@kernel.org>
To: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Michael Turquette <mturquette@baylibre.com>
To: Stephen Boyd <sboyd@kernel.org>
To: Rob Herring <robh+dt@kernel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

Abel Vesa (9):
  dt-bindings: clock: Add SM8550 GCC clock bindings
  clk: qcom: gdsc: Add configurable poll timeout
  clk: qcom: Add LUCID_OLE PLL type for SM8550
  clk: qcom: Add clock driver for SM8550
  dt-bindings: clock: Add RPMHCC bindings for SM8550
  dt-bindings: clock: qcom,rpmh: Add CXO PAD clock IDs
  clk: qcom: rpmh: Add support for SM8550 rpmh clocks
  dt-bindings: clock: Add SM8550 TCSR CC clock bindings
  clk: qcom: Add TCSR clock driver for SM8550

 .../bindings/clock/qcom,gcc-sm8550.yaml       |   88 +
 .../bindings/clock/qcom,rpmhcc.yaml           |    1 +
 .../bindings/clock/qcom,tcsrcc-sm8550.yaml    |   46 +
 drivers/clk/qcom/Kconfig                      |   15 +
 drivers/clk/qcom/Makefile                     |    2 +
 drivers/clk/qcom/clk-alpha-pll.c              |   16 +
 drivers/clk/qcom/clk-alpha-pll.h              |    5 +
 drivers/clk/qcom/clk-rpmh.c                   |  110 +-
 drivers/clk/qcom/gcc-sm8550.c                 | 3396 +++++++++++++++++
 drivers/clk/qcom/gdsc.c                       |    5 +-
 drivers/clk/qcom/gdsc.h                       |    1 +
 drivers/clk/qcom/tcsrcc-sm8550.c              |  193 +
 include/dt-bindings/clock/qcom,gcc-sm8550.h   |  231 ++
 include/dt-bindings/clock/qcom,rpmh.h         |    2 +
 .../dt-bindings/clock/qcom,tcsrcc-sm8550.h    |   18 +
 15 files changed, 4108 insertions(+), 21 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8550.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,tcsrcc-sm8550.yaml
 create mode 100644 drivers/clk/qcom/gcc-sm8550.c
 create mode 100644 drivers/clk/qcom/tcsrcc-sm8550.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8550.h
 create mode 100644 include/dt-bindings/clock/qcom,tcsrcc-sm8550.h

Comments

Konrad Dybcio Nov. 16, 2022, 11:23 a.m. UTC | #1 
On 16/11/2022 11:47, Abel Vesa wrote:
> Add a LUCID_OLE PLL type for SM8550 SoC from Qualcomm.
> 
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>   drivers/clk/qcom/clk-alpha-pll.c | 16 ++++++++++++++++
>   drivers/clk/qcom/clk-alpha-pll.h |  5 +++++
>   2 files changed, 21 insertions(+)
> 
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 1973d79c9465..f9e4cfd7261c 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -155,6 +155,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
>   		[PLL_OFF_TEST_CTL_U] = 0x30,
>   		[PLL_OFF_TEST_CTL_U1] = 0x34,
>   	},
> +	[CLK_ALPHA_PLL_TYPE_LUCID_OLE] = {
> +		[PLL_OFF_OPMODE] = 0x04,
> +		[PLL_OFF_STATE] = 0x08,
> +		[PLL_OFF_STATUS] = 0x0c,
> +		[PLL_OFF_L_VAL] = 0x10,
> +		[PLL_OFF_ALPHA_VAL] = 0x14,
> +		[PLL_OFF_USER_CTL] = 0x18,
> +		[PLL_OFF_USER_CTL_U] = 0x1c,
> +		[PLL_OFF_CONFIG_CTL] = 0x20,
> +		[PLL_OFF_CONFIG_CTL_U] = 0x24,
> +		[PLL_OFF_CONFIG_CTL_U1] = 0x28,
> +		[PLL_OFF_TEST_CTL] = 0x2c,
> +		[PLL_OFF_TEST_CTL_U] = 0x30,
> +		[PLL_OFF_TEST_CTL_U1] = 0x34,
> +		[PLL_OFF_TEST_CTL_U2] = 0x38,
> +	},
>   	[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
>   		[PLL_OFF_OPMODE] = 0x04,
>   		[PLL_OFF_STATUS] = 0x0c,
> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> index f9524b3fce6b..2bdae362c827 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.h
> +++ b/drivers/clk/qcom/clk-alpha-pll.h
> @@ -18,6 +18,7 @@ enum {
>   	CLK_ALPHA_PLL_TYPE_AGERA,
>   	CLK_ALPHA_PLL_TYPE_ZONDA,
>   	CLK_ALPHA_PLL_TYPE_LUCID_EVO,
> +	CLK_ALPHA_PLL_TYPE_LUCID_OLE,
>   	CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
>   	CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
>   	CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
> @@ -38,6 +39,8 @@ enum {
>   	PLL_OFF_TEST_CTL,
>   	PLL_OFF_TEST_CTL_U,
>   	PLL_OFF_TEST_CTL_U1,
> +	PLL_OFF_TEST_CTL_U2,
> +	PLL_OFF_STATE,
>   	PLL_OFF_STATUS,
>   	PLL_OFF_OPMODE,
>   	PLL_OFF_FRAC,
> @@ -160,7 +163,9 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops;
>   extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
>   extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
>   extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
> +#define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops
>   extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
> +#define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops
>   
>   extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
>   #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
Konrad Dybcio Nov. 16, 2022, 11:29 a.m. UTC | #2 
On 16/11/2022 11:47, Abel Vesa wrote:
> The TCSR clock controller found on SM8550 provides refclks
> for PCIE, USB and UFS. Add clock driver for it.
> 
> This patch is based on initial code downstream.
> 
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>   drivers/clk/qcom/Kconfig         |   7 ++
>   drivers/clk/qcom/Makefile        |   1 +
>   drivers/clk/qcom/tcsrcc-sm8550.c | 193 +++++++++++++++++++++++++++++++
>   3 files changed, 201 insertions(+)
>   create mode 100644 drivers/clk/qcom/tcsrcc-sm8550.c
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 7186faf70562..653049b08a25 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -788,6 +788,13 @@ config SM_GPUCC_8350
>   	  Say Y if you want to support graphics controller devices and
>   	  functionality such as 3D graphics.
>   
> +config SM_TCSRCC_8550
> +	tristate "SM8550 TCSR Clock Controller"
> +	select QCOM_GDSC
> +	help
> +	  Support for the TCSR clock controller on SM8550 devices.
> +	  Say Y if you want to use peripheral devices such as SD/UFS.
> +
>   config SM_VIDEOCC_8150
>   	tristate "SM8150 Video Clock Controller"
>   	select SM_GCC_8150
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index dc4b803d3f3d..17d878482a45 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -111,6 +111,7 @@ obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
>   obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
>   obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
>   obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
> +obj-$(CONFIG_SM_TCSRCC_8550) += tcsrcc-sm8550.o
>   obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
>   obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
>   obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
> diff --git a/drivers/clk/qcom/tcsrcc-sm8550.c b/drivers/clk/qcom/tcsrcc-sm8550.c
> new file mode 100644
> index 000000000000..3e6756da1e83
> --- /dev/null
> +++ b/drivers/clk/qcom/tcsrcc-sm8550.c
> @@ -0,0 +1,193 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2022, Linaro Limited
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,tcsrcc-sm8550.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "common.h"
> +#include "reset.h"
> +
> +enum {
> +	DT_BI_TCXO,
> +	DT_BI_TCXO_PAD,
> +};
> +
> +static struct clk_branch tcsr_pcie_0_clkref_en = {
> +	.halt_reg = 0x15100,
> +	.halt_check = BRANCH_HALT_SKIP,
> +	.clkr = {
> +		.enable_reg = 0x15100,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "tcsr_pcie_0_clkref_en",
> +			.parent_data = &(const struct clk_parent_data){
> +				.index = DT_BI_TCXO,
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch tcsr_pcie_1_clkref_en = {
> +	.halt_reg = 0x15114,
> +	.halt_check = BRANCH_HALT_SKIP,
> +	.clkr = {
> +		.enable_reg = 0x15114,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "tcsr_pcie_1_clkref_en",
> +			.parent_data = &(const struct clk_parent_data){
> +				.index = DT_BI_TCXO,
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch tcsr_ufs_clkref_en = {
> +	.halt_reg = 0x15110,
> +	.halt_check = BRANCH_HALT_SKIP,
> +	.clkr = {
> +		.enable_reg = 0x15110,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "tcsr_ufs_clkref_en",
> +			.parent_data = &(const struct clk_parent_data){
> +				.index = DT_BI_TCXO,
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch tcsr_ufs_pad_clkref_en = {
> +	.halt_reg = 0x15104,
> +	.halt_check = BRANCH_HALT_SKIP,
> +	.clkr = {
> +		.enable_reg = 0x15104,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "tcsr_ufs_pad_clkref_en",
> +			.parent_data = &(const struct clk_parent_data){
> +				.index = DT_BI_TCXO,
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch tcsr_usb2_clkref_en = {
> +	.halt_reg = 0x15118,
> +	.halt_check = BRANCH_HALT_SKIP,
> +	.clkr = {
> +		.enable_reg = 0x15118,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "tcsr_usb2_clkref_en",
> +			.parent_data = &(const struct clk_parent_data){
> +				.index = DT_BI_TCXO_PAD,
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch tcsr_usb3_clkref_en = {
> +	.halt_reg = 0x15108,
> +	.halt_check = BRANCH_HALT_SKIP,
> +	.clkr = {
> +		.enable_reg = 0x15108,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "tcsr_usb3_clkref_en",
> +			.parent_data = &(const struct clk_parent_data){
> +				.index = DT_BI_TCXO,
> +			},
> +			.num_parents = 1,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_regmap *tcsr_cc_sm8550_clocks[] = {
> +	[TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr,
> +	[TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr,
> +	[TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr,
> +	[TCSR_UFS_PAD_CLKREF_EN] = &tcsr_ufs_pad_clkref_en.clkr,
> +	[TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr,
> +	[TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr,
> +};
> +
> +static const struct regmap_config tcsr_cc_sm8550_regmap_config = {
> +	.reg_bits = 32,
> +	.reg_stride = 4,
> +	.val_bits = 32,
> +	.max_register = 0x2f000,
> +	.fast_io = true,
> +};
> +
> +static const struct qcom_cc_desc tcsr_cc_sm8550_desc = {
> +	.config = &tcsr_cc_sm8550_regmap_config,
> +	.clks = tcsr_cc_sm8550_clocks,
> +	.num_clks = ARRAY_SIZE(tcsr_cc_sm8550_clocks),
> +};
> +
> +static const struct of_device_id tcsr_cc_sm8550_match_table[] = {
> +	{ .compatible = "qcom,sm8550-tcsrcc" },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, tcsr_cc_sm8550_match_table);
> +
> +static int tcsr_cc_sm8550_probe(struct platform_device *pdev)
> +{
> +	struct regmap *regmap;
> +
> +	regmap = qcom_cc_map(pdev, &tcsr_cc_sm8550_desc);
> +	if (IS_ERR(regmap))
> +		return PTR_ERR(regmap);
> +
> +	return qcom_cc_really_probe(pdev, &tcsr_cc_sm8550_desc, regmap);
> +}
> +
> +static struct platform_driver tcsr_cc_sm8550_driver = {
> +	.probe = tcsr_cc_sm8550_probe,
> +	.driver = {
> +		.name = "tcsr_cc-sm8550",
> +		.of_match_table = tcsr_cc_sm8550_match_table,
> +	},
> +};
> +
> +static int __init tcsr_cc_sm8550_init(void)
> +{
> +	return platform_driver_register(&tcsr_cc_sm8550_driver);
> +}
> +subsys_initcall(tcsr_cc_sm8550_init);
> +
> +static void __exit tcsr_cc_sm8550_exit(void)
> +{
> +	platform_driver_unregister(&tcsr_cc_sm8550_driver);
> +}
> +module_exit(tcsr_cc_sm8550_exit);
> +
> +MODULE_DESCRIPTION("QTI TCSRCC SM8550 Driver");
> +MODULE_LICENSE("GPL");
Abel Vesa Nov. 17, 2022, 9:40 a.m. UTC | #3 
On 22-11-17 10:08:05, Krzysztof Kozlowski wrote:
> On 16/11/2022 11:47, Abel Vesa wrote:
> > Add device tree bindings for global clock controller on SM8550 SoCs.
> 
> Subject: drop second, redundant "bindings".

Sure thing, will drop.

> 
> > 
> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > ---
> >  .../bindings/clock/qcom,gcc-sm8550.yaml       |  88 +++++++
> >  include/dt-bindings/clock/qcom,gcc-sm8550.h   | 231 ++++++++++++++++++
> >  2 files changed, 319 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8550.yaml
> >  create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8550.h
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8550.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8550.yaml
> > new file mode 100644
> > index 000000000000..a2468167c8ab
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8550.yaml
> > @@ -0,0 +1,88 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8550.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm Global Clock & Reset Controller Binding for SM8550
> 
> You need to base on recent bindings. See commit ece3c3198182a1.
> 

Yep, will do.

> > +
> > +maintainers:
> > +  - Bjorn Andersson <andersson@kernel.org>
> > +
> > +description: |
> > +  Qualcomm global clock control module which supports the clocks, resets and
> > +  power domains on SM8550
> 
> Ditto
> 
> > +
> > +  See also:
> > +  - dt-bindings/clock/qcom,gcc-sm8550.h
> 
> Ditto
> 
> > +
> > +properties:
> > +  compatible:
> > +    const: qcom,sm8550-gcc
> > +
> > +  clocks:
> > +    items:
> > +      - description: Board XO source
> > +      - description: Sleep clock source
> > +      - description: PCIE 0 Pipe clock source (Optional clock)
> 
> Drop "(Optional clock)"

Sure, will drop. I based this on SM8450, but maybe that also needs an
update.

> 
> > +      - description: PCIE 1 Pipe clock source (Optional clock)
> > +      - description: PCIE 1 Phy Auxiliary clock source (Optional clock)
> > +      - description: UFS Phy Rx symbol 0 clock source (Optional clock)
> > +      - description: UFS Phy Rx symbol 1 clock source (Optional clock)
> > +      - description: UFS Phy Tx symbol 0 clock source (Optional clock)
> > +      - description: USB3 Phy wrapper pipe clock source (Optional clock)
> > +    minItems: 2
> 
> This does not look correct. Why clocks of GCC are inputs clocks to GCC?

Well, it is not a GCC clock. It is a fixed-clock fed into GCC.
The name is taken from downstream, but I'm pretty sure the HW clock is
named so. So I think we should keep it as is.

> 
> > +
> > +  clock-names:
> > +    items:
> > +      - const: bi_tcxo
> > +      - const: sleep_clk
> > +      - const: pcie_0_pipe_clk # Optional clock
> > +      - const: pcie_1_pipe_clk # Optional clock
> > +      - const: pcie_1_phy_aux_clk # Optional clock
> > +      - const: ufs_phy_rx_symbol_0_clk # Optional clock
> > +      - const: ufs_phy_rx_symbol_1_clk # Optional clock
> > +      - const: ufs_phy_tx_symbol_0_clk # Optional clock
> > +      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
> > +    minItems: 2
> > +
> > +  '#clock-cells':
> > +    const: 1
> > +
> > +  '#reset-cells':
> > +    const: 1
> > +
> > +  '#power-domain-cells':
> > +    const: 1
> > +
> > +  reg:
> > +    maxItems: 1
> 
> Drop all duplicated properties and use qcom,gcc.yaml. See commit
> 842b4ca1cb8cf54
> 

Will do.

> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +  - '#clock-cells'
> > +  - '#reset-cells'
> > +  - '#power-domain-cells'
> 
> Drop redundant entries.

Will do.

> 
> > +
> > +allOf:
> > +  - $ref: qcom,gcc.yaml#
> > +
> 

Thanks,
Abel

> Best regards,
> Krzysztof
>
Krzysztof Kozlowski Nov. 17, 2022, 10:27 a.m. UTC | #4 
On 17/11/2022 10:40, Abel Vesa wrote:
> On 22-11-17 10:08:05, Krzysztof Kozlowski wrote:
>> On 16/11/2022 11:47, Abel Vesa wrote:
>>> Add device tree bindings for global clock controller on SM8550 SoCs.
>>
>> Subject: drop second, redundant "bindings".
> 
> Sure thing, will drop.
> 
>>
>>>
>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
>>> ---
>>>  .../bindings/clock/qcom,gcc-sm8550.yaml       |  88 +++++++
>>>  include/dt-bindings/clock/qcom,gcc-sm8550.h   | 231 ++++++++++++++++++
>>>  2 files changed, 319 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8550.yaml
>>>  create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8550.h
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8550.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8550.yaml
>>> new file mode 100644
>>> index 000000000000..a2468167c8ab
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8550.yaml
>>> @@ -0,0 +1,88 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8550.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Qualcomm Global Clock & Reset Controller Binding for SM8550
>>
>> You need to base on recent bindings. See commit ece3c3198182a1.
>>
> 
> Yep, will do.
> 
>>> +
>>> +maintainers:
>>> +  - Bjorn Andersson <andersson@kernel.org>
>>> +
>>> +description: |
>>> +  Qualcomm global clock control module which supports the clocks, resets and
>>> +  power domains on SM8550
>>
>> Ditto
>>
>>> +
>>> +  See also:
>>> +  - dt-bindings/clock/qcom,gcc-sm8550.h
>>
>> Ditto
>>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: qcom,sm8550-gcc
>>> +
>>> +  clocks:
>>> +    items:
>>> +      - description: Board XO source
>>> +      - description: Sleep clock source
>>> +      - description: PCIE 0 Pipe clock source (Optional clock)
>>
>> Drop "(Optional clock)"
> 
> Sure, will drop. I based this on SM8450, but maybe that also needs an
> update.
> 
>>
>>> +      - description: PCIE 1 Pipe clock source (Optional clock)
>>> +      - description: PCIE 1 Phy Auxiliary clock source (Optional clock)
>>> +      - description: UFS Phy Rx symbol 0 clock source (Optional clock)
>>> +      - description: UFS Phy Rx symbol 1 clock source (Optional clock)
>>> +      - description: UFS Phy Tx symbol 0 clock source (Optional clock)
>>> +      - description: USB3 Phy wrapper pipe clock source (Optional clock)
>>> +    minItems: 2
>>
>> This does not look correct. Why clocks of GCC are inputs clocks to GCC?
> 
> Well, it is not a GCC clock. It is a fixed-clock fed into GCC.
> The name is taken from downstream, but I'm pretty sure the HW clock is
> named so. So I think we should keep it as is.

I don't get it. The "PCIE 0 Pipe clock source" is defined here in this
header:
+#define GCC_PCIE_0_PIPE_CLK_SRC	41
so what do you mean it is not GCC clock?

Second thing, you have only one GCC, so how these clocks can be
optional? Either they are there or they are not. Optional means usually
that you have two devices having same compatible and they can operate a
bit differently or some pins are not connected. It's not the case here.

Best regards,
Krzysztof