mbox series

[V3,0/5] Add regulator support for IPQ9574 SoC

Message ID 20230406070032.22243-1-quic_devipriy@quicinc.com
Headers show
Series Add regulator support for IPQ9574 SoC | expand

Message

Devi Priya April 6, 2023, 7 a.m. UTC 
IPQ9574 SoC uses the PMIC MP5496 and SMPA1 regulator for APSS voltage scaling.
This patch series adds support for the same and also enables the RPM 
communication over the RPMSG framework.

DTS patch depends on the below series
https://lore.kernel.org/linux-arm-msm/20230406061314.10916-1-quic_devipriy@quicinc.com/

[V3]:
	- Dropped PATCH [1/6] dt-bindings: soc: qcom: smd-rpm: Add IPQ9574 compatible
	  as it is available in linux-next/master
	- Dropped PATCH [4/6] regulator: qcom_smd: Add support to define the bootup voltage
	  and updated the nominal voltage in the Board DT as discussed
	- Splitted the board DT changes to a separate patch as suggested
	- Detailed change logs are added to the respective patches
[V2]:
	https://lore.kernel.org/linux-arm-msm/20230217142030.16012-1-quic_devipriy@quicinc.com/
	- Reordered the patches to have the bindings and driver changes
	  in place before the device tree support
	- Dropped the 'soc: qcom: smd-rpm: Add IPQ9574 compatible' since
	  it is already part of the linux-next/master
	- Detailed change log is added to the respective patches
[V1]:
	https://lore.kernel.org/linux-arm-msm/20230113150310.29709-1-quic_devipriy@quicinc.com/

Devi Priya (5):
  regulator: qcom_smd: Add s1 sub-node to mp5496 regulator
  regulator: qcom_smd: Add MP5496 S1 regulator
  arm64: dts: qcom: ipq9574: Add RPM related nodes
  arm64: dts: qcom: ipq9574: Add SMPA1 regulator node
  arm64: dts: qcom: ipq9574: Add cpufreq support

 .../regulator/qcom,smd-rpm-regulator.yaml     |  2 +-
 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts   | 19 +++++
 arch/arm64/boot/dts/qcom/ipq9574.dtsi         | 75 +++++++++++++++++++
 drivers/regulator/qcom_smd-regulator.c        | 10 +++
 4 files changed, 105 insertions(+), 1 deletion(-)


base-commit: 8417c8f5007bf4567ccffda850a3157c7d905f67

Comments

Konrad Dybcio April 6, 2023, 7:37 p.m. UTC | #1 
On 6.04.2023 09:00, Devi Priya wrote:
> Add RPM Glink & RPM message RAM nodes to support frequency scaling
> on IPQ9574.
> 
> Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  Changes in V3:
> 	- Moved rpm_msg_ram node under /soc and updated the node name to sram@
> 	- Moved rpm-glink node such that the nodes are sorted alphabetically
> 
>  arch/arm64/boot/dts/qcom/ipq9574.dtsi | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 7c820463a79d..1f9b7529e7ed 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -110,12 +110,29 @@
>  		};
>  	};
>  
> +	rpm-glink {
> +		compatible = "qcom,glink-rpm";
> +		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
> +		qcom,rpm-msg-ram = <&rpm_msg_ram>;
> +		mboxes = <&apcs_glb 0>;
> +
> +		rpm_requests: rpm-requests {
> +			compatible = "qcom,rpm-ipq9574";
> +			qcom,glink-channels = "rpm_requests";
> +		};
> +	};
> +
>  	soc: soc@0 {
>  		compatible = "simple-bus";
>  		#address-cells = <1>;
>  		#size-cells = <1>;
>  		ranges = <0 0 0 0xffffffff>;
>  
> +		rpm_msg_ram: sram@60000 {
> +			compatible = "qcom,rpm-msg-ram";
> +			reg = <0x00060000 0x6000>;
> +		};
> +
>  		pcie0_phy: phy@84000 {
>  			compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
>  			reg = <0x00084000 0x1000>;
Konrad Dybcio April 6, 2023, 7:51 p.m. UTC | #2 
On 6.04.2023 09:00, Devi Priya wrote:
> Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz.
> 
> Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
>  Changes in V3:
> 	- No change
> 
>  arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++
>  1 file changed, 58 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 1f9b7529e7ed..cfef87b5fd22 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -6,6 +6,7 @@
>   * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>   */
>  
> +#include <dt-bindings/clock/qcom,apss-ipq.h>
>  #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
> @@ -37,6 +38,10 @@
>  			reg = <0x0>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_0>;
> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> +			clock-names = "cpu";
> +			operating-points-v2 = <&cpu_opp_table>;
> +			cpu-supply = <&ipq9574_s1>;
>  		};
>  
>  		CPU1: cpu@1 {
> @@ -45,6 +50,10 @@
>  			reg = <0x1>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_0>;
> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> +			clock-names = "cpu";
> +			operating-points-v2 = <&cpu_opp_table>;
> +			cpu-supply = <&ipq9574_s1>;
>  		};
>  
>  		CPU2: cpu@2 {
> @@ -53,6 +62,10 @@
>  			reg = <0x2>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_0>;
> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> +			clock-names = "cpu";
> +			operating-points-v2 = <&cpu_opp_table>;
> +			cpu-supply = <&ipq9574_s1>;
>  		};
>  
>  		CPU3: cpu@3 {
> @@ -61,6 +74,10 @@
>  			reg = <0x3>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_0>;
> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> +			clock-names = "cpu";
> +			operating-points-v2 = <&cpu_opp_table>;
> +			cpu-supply = <&ipq9574_s1>;
>  		};
>  
>  		L2_0: l2-cache {
> @@ -75,6 +92,47 @@
>  		reg = <0x0 0x40000000 0x0 0x0>;
>  	};
>  
> +	cpu_opp_table: opp-table-cpu {
This is not sorted properly. It should probably come
after memory alphabetically ('o' > 'm')

Konrad
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp-936000000 {
> +			opp-hz = /bits/ 64 <936000000>;
> +			opp-microvolt = <725000>;
> +			clock-latency-ns = <200000>;
> +		};
> +
> +		opp-1104000000 {
> +			opp-hz = /bits/ 64 <1104000000>;
> +			opp-microvolt = <787500>;
> +			clock-latency-ns = <200000>;
> +		};
> +
> +		opp-1416000000 {
> +			opp-hz = /bits/ 64 <1416000000>;
> +			opp-microvolt = <862500>;
> +			clock-latency-ns = <200000>;
> +		};
> +
> +		opp-1488000000 {
> +			opp-hz = /bits/ 64 <1488000000>;
> +			opp-microvolt = <925000>;
> +			clock-latency-ns = <200000>;
> +		};
> +
> +		opp-1800000000 {
> +			opp-hz = /bits/ 64 <1800000000>;
> +			opp-microvolt = <987500>;
> +			clock-latency-ns = <200000>;
> +		};
> +
> +		opp-2208000000 {
> +			opp-hz = /bits/ 64 <2208000000>;
> +			opp-microvolt = <1062500>;
> +			clock-latency-ns = <200000>;
> +		};
> +	};
> +
>  	firmware {
>  		scm {
>  			compatible = "qcom,scm-ipq9574", "qcom,scm";
Devi Priya April 7, 2023, 4:53 a.m. UTC | #3 
On 4/7/2023 1:21 AM, Konrad Dybcio wrote:
> 
> 
> On 6.04.2023 09:00, Devi Priya wrote:
>> Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz.
>>
>> Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
>> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
>>   Changes in V3:
>> 	- No change
>>
>>   arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++
>>   1 file changed, 58 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 1f9b7529e7ed..cfef87b5fd22 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -6,6 +6,7 @@
>>    * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>>    */
>>   
>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
>>   #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>> @@ -37,6 +38,10 @@
>>   			reg = <0x0>;
>>   			enable-method = "psci";
>>   			next-level-cache = <&L2_0>;
>> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>> +			clock-names = "cpu";
>> +			operating-points-v2 = <&cpu_opp_table>;
>> +			cpu-supply = <&ipq9574_s1>;
>>   		};
>>   
>>   		CPU1: cpu@1 {
>> @@ -45,6 +50,10 @@
>>   			reg = <0x1>;
>>   			enable-method = "psci";
>>   			next-level-cache = <&L2_0>;
>> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>> +			clock-names = "cpu";
>> +			operating-points-v2 = <&cpu_opp_table>;
>> +			cpu-supply = <&ipq9574_s1>;
>>   		};
>>   
>>   		CPU2: cpu@2 {
>> @@ -53,6 +62,10 @@
>>   			reg = <0x2>;
>>   			enable-method = "psci";
>>   			next-level-cache = <&L2_0>;
>> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>> +			clock-names = "cpu";
>> +			operating-points-v2 = <&cpu_opp_table>;
>> +			cpu-supply = <&ipq9574_s1>;
>>   		};
>>   
>>   		CPU3: cpu@3 {
>> @@ -61,6 +74,10 @@
>>   			reg = <0x3>;
>>   			enable-method = "psci";
>>   			next-level-cache = <&L2_0>;
>> +			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>> +			clock-names = "cpu";
>> +			operating-points-v2 = <&cpu_opp_table>;
>> +			cpu-supply = <&ipq9574_s1>;
>>   		};
>>   
>>   		L2_0: l2-cache {
>> @@ -75,6 +92,47 @@
>>   		reg = <0x0 0x40000000 0x0 0x0>;
>>   	};
>>   
>> +	cpu_opp_table: opp-table-cpu {
> This is not sorted properly. It should probably come
> after memory alphabetically ('o' > 'm')
>
Yes, But I see that opp-table-cpu node is already placed after
memory@40000000
> Konrad
>> +		compatible = "operating-points-v2";
>> +		opp-shared;
>> +
>> +		opp-936000000 {
>> +			opp-hz = /bits/ 64 <936000000>;
>> +			opp-microvolt = <725000>;
>> +			clock-latency-ns = <200000>;
>> +		};
>> +
>> +		opp-1104000000 {
>> +			opp-hz = /bits/ 64 <1104000000>;
>> +			opp-microvolt = <787500>;
>> +			clock-latency-ns = <200000>;
>> +		};
>> +
>> +		opp-1416000000 {
>> +			opp-hz = /bits/ 64 <1416000000>;
>> +			opp-microvolt = <862500>;
>> +			clock-latency-ns = <200000>;
>> +		};
>> +
>> +		opp-1488000000 {
>> +			opp-hz = /bits/ 64 <1488000000>;
>> +			opp-microvolt = <925000>;
>> +			clock-latency-ns = <200000>;
>> +		};
>> +
>> +		opp-1800000000 {
>> +			opp-hz = /bits/ 64 <1800000000>;
>> +			opp-microvolt = <987500>;
>> +			clock-latency-ns = <200000>;
>> +		};
>> +
>> +		opp-2208000000 {
>> +			opp-hz = /bits/ 64 <2208000000>;
>> +			opp-microvolt = <1062500>;
>> +			clock-latency-ns = <200000>;
>> +		};
>> +	};
>> +
>>   	firmware {
>>   		scm {
>>   			compatible = "qcom,scm-ipq9574", "qcom,scm";
Best Regards,
Devi Priya
Konrad Dybcio April 7, 2023, 11:59 a.m. UTC | #4 
On 7.04.2023 06:53, Devi Priya wrote:
> 
> 
> On 4/7/2023 1:21 AM, Konrad Dybcio wrote:
>>
>>
>> On 6.04.2023 09:00, Devi Priya wrote:
>>> Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz.
>>>
>>> Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
>>> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>>> ---
>>>   Changes in V3:
>>>     - No change
>>>
>>>   arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++
>>>   1 file changed, 58 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> index 1f9b7529e7ed..cfef87b5fd22 100644
>>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> @@ -6,6 +6,7 @@
>>>    * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>>>    */
>>>   +#include <dt-bindings/clock/qcom,apss-ipq.h>
>>>   #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>   #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>>> @@ -37,6 +38,10 @@
>>>               reg = <0x0>;
>>>               enable-method = "psci";
>>>               next-level-cache = <&L2_0>;
>>> +            clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>> +            clock-names = "cpu";
>>> +            operating-points-v2 = <&cpu_opp_table>;
>>> +            cpu-supply = <&ipq9574_s1>;
>>>           };
>>>             CPU1: cpu@1 {
>>> @@ -45,6 +50,10 @@
>>>               reg = <0x1>;
>>>               enable-method = "psci";
>>>               next-level-cache = <&L2_0>;
>>> +            clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>> +            clock-names = "cpu";
>>> +            operating-points-v2 = <&cpu_opp_table>;
>>> +            cpu-supply = <&ipq9574_s1>;
>>>           };
>>>             CPU2: cpu@2 {
>>> @@ -53,6 +62,10 @@
>>>               reg = <0x2>;
>>>               enable-method = "psci";
>>>               next-level-cache = <&L2_0>;
>>> +            clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>> +            clock-names = "cpu";
>>> +            operating-points-v2 = <&cpu_opp_table>;
>>> +            cpu-supply = <&ipq9574_s1>;
>>>           };
>>>             CPU3: cpu@3 {
>>> @@ -61,6 +74,10 @@
>>>               reg = <0x3>;
>>>               enable-method = "psci";
>>>               next-level-cache = <&L2_0>;
>>> +            clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>> +            clock-names = "cpu";
>>> +            operating-points-v2 = <&cpu_opp_table>;
>>> +            cpu-supply = <&ipq9574_s1>;
>>>           };
>>>             L2_0: l2-cache {
>>> @@ -75,6 +92,47 @@
>>>           reg = <0x0 0x40000000 0x0 0x0>;
>>>       };
>>>   +    cpu_opp_table: opp-table-cpu {
>> This is not sorted properly. It should probably come
>> after memory alphabetically ('o' > 'm')
>>
> Yes, But I see that opp-table-cpu node is already placed after
> memory@40000000

Oh you're right, the diff doesn't really show that very
well and I didn't notice..


Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>> Konrad
>>> +        compatible = "operating-points-v2";
>>> +        opp-shared;
>>> +
>>> +        opp-936000000 {
>>> +            opp-hz = /bits/ 64 <936000000>;
>>> +            opp-microvolt = <725000>;
>>> +            clock-latency-ns = <200000>;
>>> +        };
>>> +
>>> +        opp-1104000000 {
>>> +            opp-hz = /bits/ 64 <1104000000>;
>>> +            opp-microvolt = <787500>;
>>> +            clock-latency-ns = <200000>;
>>> +        };
>>> +
>>> +        opp-1416000000 {
>>> +            opp-hz = /bits/ 64 <1416000000>;
>>> +            opp-microvolt = <862500>;
>>> +            clock-latency-ns = <200000>;
>>> +        };
>>> +
>>> +        opp-1488000000 {
>>> +            opp-hz = /bits/ 64 <1488000000>;
>>> +            opp-microvolt = <925000>;
>>> +            clock-latency-ns = <200000>;
>>> +        };
>>> +
>>> +        opp-1800000000 {
>>> +            opp-hz = /bits/ 64 <1800000000>;
>>> +            opp-microvolt = <987500>;
>>> +            clock-latency-ns = <200000>;
>>> +        };
>>> +
>>> +        opp-2208000000 {
>>> +            opp-hz = /bits/ 64 <2208000000>;
>>> +            opp-microvolt = <1062500>;
>>> +            clock-latency-ns = <200000>;
>>> +        };
>>> +    };
>>> +
>>>       firmware {
>>>           scm {
>>>               compatible = "qcom,scm-ipq9574", "qcom,scm";
> Best Regards,
> Devi Priya
Devi Priya April 7, 2023, 2:24 p.m. UTC | #5 
On 4/7/2023 5:29 PM, Konrad Dybcio wrote:
> 
> 
> On 7.04.2023 06:53, Devi Priya wrote:
>>
>>
>> On 4/7/2023 1:21 AM, Konrad Dybcio wrote:
>>>
>>>
>>> On 6.04.2023 09:00, Devi Priya wrote:
>>>> Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz.
>>>>
>>>> Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
>>>> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
>>>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>>>> ---
>>>>    Changes in V3:
>>>>      - No change
>>>>
>>>>    arch/arm64/boot/dts/qcom/ipq9574.dtsi | 58 +++++++++++++++++++++++++++
>>>>    1 file changed, 58 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>> index 1f9b7529e7ed..cfef87b5fd22 100644
>>>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>> @@ -6,6 +6,7 @@
>>>>     * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>>>>     */
>>>>    +#include <dt-bindings/clock/qcom,apss-ipq.h>
>>>>    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>>>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>>    #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>>>> @@ -37,6 +38,10 @@
>>>>                reg = <0x0>;
>>>>                enable-method = "psci";
>>>>                next-level-cache = <&L2_0>;
>>>> +            clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>>> +            clock-names = "cpu";
>>>> +            operating-points-v2 = <&cpu_opp_table>;
>>>> +            cpu-supply = <&ipq9574_s1>;
>>>>            };
>>>>              CPU1: cpu@1 {
>>>> @@ -45,6 +50,10 @@
>>>>                reg = <0x1>;
>>>>                enable-method = "psci";
>>>>                next-level-cache = <&L2_0>;
>>>> +            clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>>> +            clock-names = "cpu";
>>>> +            operating-points-v2 = <&cpu_opp_table>;
>>>> +            cpu-supply = <&ipq9574_s1>;
>>>>            };
>>>>              CPU2: cpu@2 {
>>>> @@ -53,6 +62,10 @@
>>>>                reg = <0x2>;
>>>>                enable-method = "psci";
>>>>                next-level-cache = <&L2_0>;
>>>> +            clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>>> +            clock-names = "cpu";
>>>> +            operating-points-v2 = <&cpu_opp_table>;
>>>> +            cpu-supply = <&ipq9574_s1>;
>>>>            };
>>>>              CPU3: cpu@3 {
>>>> @@ -61,6 +74,10 @@
>>>>                reg = <0x3>;
>>>>                enable-method = "psci";
>>>>                next-level-cache = <&L2_0>;
>>>> +            clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
>>>> +            clock-names = "cpu";
>>>> +            operating-points-v2 = <&cpu_opp_table>;
>>>> +            cpu-supply = <&ipq9574_s1>;
>>>>            };
>>>>              L2_0: l2-cache {
>>>> @@ -75,6 +92,47 @@
>>>>            reg = <0x0 0x40000000 0x0 0x0>;
>>>>        };
>>>>    +    cpu_opp_table: opp-table-cpu {
>>> This is not sorted properly. It should probably come
>>> after memory alphabetically ('o' > 'm')
>>>
>> Yes, But I see that opp-table-cpu node is already placed after
>> memory@40000000
> 
> Oh you're right, the diff doesn't really show that very
> well and I didn't notice..
> 
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Sure, thank you!
> 
> Konrad
>>> Konrad
>>>> +        compatible = "operating-points-v2";
>>>> +        opp-shared;
>>>> +
>>>> +        opp-936000000 {
>>>> +            opp-hz = /bits/ 64 <936000000>;
>>>> +            opp-microvolt = <725000>;
>>>> +            clock-latency-ns = <200000>;
>>>> +        };
>>>> +
>>>> +        opp-1104000000 {
>>>> +            opp-hz = /bits/ 64 <1104000000>;
>>>> +            opp-microvolt = <787500>;
>>>> +            clock-latency-ns = <200000>;
>>>> +        };
>>>> +
>>>> +        opp-1416000000 {
>>>> +            opp-hz = /bits/ 64 <1416000000>;
>>>> +            opp-microvolt = <862500>;
>>>> +            clock-latency-ns = <200000>;
>>>> +        };
>>>> +
>>>> +        opp-1488000000 {
>>>> +            opp-hz = /bits/ 64 <1488000000>;
>>>> +            opp-microvolt = <925000>;
>>>> +            clock-latency-ns = <200000>;
>>>> +        };
>>>> +
>>>> +        opp-1800000000 {
>>>> +            opp-hz = /bits/ 64 <1800000000>;
>>>> +            opp-microvolt = <987500>;
>>>> +            clock-latency-ns = <200000>;
>>>> +        };
>>>> +
>>>> +        opp-2208000000 {
>>>> +            opp-hz = /bits/ 64 <2208000000>;
>>>> +            opp-microvolt = <1062500>;
>>>> +            clock-latency-ns = <200000>;
>>>> +        };
>>>> +    };
>>>> +
>>>>        firmware {
>>>>            scm {
>>>>                compatible = "qcom,scm-ipq9574", "qcom,scm";
>> Best Regards,
>> Devi Priya