| Message ID | 20230411130446.401440-1-brgl@bgdev.pl |
|---|---|
| Headers | show |
| Series | arm64: qcom: sa8775p: add support for UFS | expand |
On Tue, 11 Apr 2023 15:04:41 +0200, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Update relevant DT bindings, add new config to the driver and add UFS > and PHY nodes to the .dtsi and enable them in the board .dts for > sa8775p-ride. > > v2 -> v3: > - fix DT bindings: move allOf: below required: > - collect review tags > > [...] Applied, thanks! [4/5] arm64: dts: qcom: sa8775p: add UFS nodes commit: be543efeee17b93edaac61e49c6361d2209bd3d3 [5/5] arm64: dts: qcom: sa8775p-ride: enable UFS commit: 35c45a1125fc0772b95aa41acc25deddcf5492be Best regards,
On Tue, Apr 11, 2023 at 03:04:45PM +0200, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Add nodes for the UFS and its PHY on sa8775p platforms. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 58 +++++++++++++++++++++++++++ > 1 file changed, 58 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 2343df7e0ea4..5de0fbbe9752 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -585,6 +585,64 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > }; > }; > > + ufs_mem_hc: ufs@1d84000 { > + compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; > + reg = <0x0 0x01d84000 0x0 0x3000>; > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&ufs_mem_phy>; > + phy-names = "ufsphy"; > + lanes-per-direction = <2>; > + #reset-cells = <1>; > + resets = <&gcc GCC_UFS_PHY_BCR>; > + reset-names = "rst"; > + power-domains = <&gcc UFS_PHY_GDSC>; > + required-opps = <&rpmhpd_opp_nom>; > + iommus = <&apps_smmu 0x100 0x0>; > + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > + <&gcc GCC_UFS_PHY_AHB_CLK>, > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; > + clock-names = "core_clk", > + "bus_aggr_clk", > + "iface_clk", > + "core_clk_unipro", > + "ref_clk", > + "tx_lane0_sync_clk", > + "rx_lane0_sync_clk", > + "rx_lane1_sync_clk"; > + freq-table-hz = <75000000 300000000>, > + <0 0>, > + <0 0>, > + <75000000 300000000>, > + <0 0>, > + <0 0>, > + <0 0>, > + <0 0>; > + status = "disabled"; I'm pretty sure that the UFS controllers found in latest SoCs are cache coherent. So you'd need "dma-coherent" property here. - Mani > + }; > + > + ufs_mem_phy: phy@1d87000 { > + compatible = "qcom,sa8775p-qmp-ufs-phy"; > + reg = <0x0 0x01d87000 0x0 0xe10>; > + /* > + * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It > + * enables the CXO clock to eDP *and* UFS PHY. > + */ > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, > + <&gcc GCC_EDP_REF_CLKREF_EN>; > + clock-names = "ref", "ref_aux", "qref"; > + power-domains = <&gcc UFS_PHY_GDSC>; > + resets = <&ufs_mem_hc 0>; > + reset-names = "ufsphy"; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x0 0x01f40000 0x0 0x20000>; > -- > 2.37.2 >
On Tue, Apr 11, 2023 at 3:04 PM Bartosz Golaszewski <brgl@bgdev.pl> wrote: > > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Add the compatible string for the UFS on sa8775p platforms. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > index c5a06c048389..b1c00424c2b0 100644 > --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml > @@ -26,6 +26,7 @@ properties: > - qcom,msm8994-ufshc > - qcom,msm8996-ufshc > - qcom,msm8998-ufshc > + - qcom,sa8775p-ufshc > - qcom,sc8280xp-ufshc > - qcom,sdm845-ufshc > - qcom,sm6350-ufshc > @@ -105,6 +106,7 @@ allOf: > contains: > enum: > - qcom,msm8998-ufshc > + - qcom,sa8775p-ufshc > - qcom,sc8280xp-ufshc > - qcom,sm8250-ufshc > - qcom,sm8350-ufshc > -- > 2.37.2 > Bjorn, Are you picking this one up as well or should it go through Rob's tree? Bart
Bartosz, > Hey UFS maintainers, could you please pick this one up for the next > merge window? Applied to 6.5/scsi-staging, thanks!
On Tue, 11 Apr 2023 15:04:41 +0200, Bartosz Golaszewski wrote: > Update relevant DT bindings, add new config to the driver and add UFS > and PHY nodes to the .dtsi and enable them in the board .dts for > sa8775p-ride. > > v2 -> v3: > - fix DT bindings: move allOf: below required: > - collect review tags > > [...] Applied to 6.5/scsi-queue, thanks! [1/5] dt-bindings: ufs: qcom: add compatible for sa8775p https://git.kernel.org/mkp/scsi/c/8f0c17bf6bf3
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Update relevant DT bindings, add new config to the driver and add UFS and PHY nodes to the .dtsi and enable them in the board .dts for sa8775p-ride. v2 -> v3: - fix DT bindings: move allOf: below required: - collect review tags v1 -> v2: - order new compatibles alphabetically - rework the UFS PHY bindings to accomodate more clocks - add a comment in the .dts regarding a non-standard clock used by the UFS PHY Bartosz Golaszewski (5): dt-bindings: ufs: qcom: add compatible for sa8775p dt-bindings: phy: qmp-ufs: describe the UFS PHY for sa8775p phy: qualcomm: phy-qcom-qmp-ufs: add definitions for sa8775p arm64: dts: qcom: sa8775p: add UFS nodes arm64: dts: qcom: sa8775p-ride: enable UFS .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 26 ++++++++- .../devicetree/bindings/ufs/qcom,ufs.yaml | 2 + arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 19 ++++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 58 +++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 38 ++++++++++++ 5 files changed, 142 insertions(+), 1 deletion(-)