[v2,0/3] Add support for a streaming interface for TMC ETR

Message ID	20230813151253.38128-1-quic_jinlmao@quicinc.com
Headers	show Return-Path: <linux-arm-msm-owner@vger.kernel.org> From: Mao Jinlong <quic_jinlmao@quicinc.com> To: Suzuki K Poulose <suzuki.poulose@arm.com>, Mike Leach <mike.leach@linaro.org>, James Clark <james.clark@arm.com>, Leo Yan <leo.yan@linaro.org>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Andy Gross <agross@kernel.org>, "Bjorn Andersson" <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org> CC: Mao Jinlong <quic_jinlmao@quicinc.com>, <coresight@lists.linaro.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>, Tingwei Zhang <quic_tingweiz@quicinc.com>, Yuanfang Zhang <quic_yuanfang@quicinc.com>, "Tao Zhang" <quic_taozha@quicinc.com>, Hao Zhang <quic_hazha@quicinc.com> Subject: [PATCH v2 0/3] Add support for a streaming interface for TMC ETR Date: Sun, 13 Aug 2023 23:12:50 +0800 Message-ID: <20230813151253.38128-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk
Series	Add support for a streaming interface for TMC ETR \| expand [v2,0/3] Add support for a streaming interface for TMC ETR [v2,1/3] Coresight: Add driver to support for CSR [v2,2/3] dt-bindings: arm: Adds CoreSight CSR hardware definitions [v2,3/3] coresight-csr: Add support for streaming interface for ETR

Message ID

20230813151253.38128-1-quic_jinlmao@quicinc.com

Headers

From: Mao Jinlong <quic_jinlmao@quicinc.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
        Mike Leach <mike.leach@linaro.org>,
        James Clark <james.clark@arm.com>,
        Leo Yan <leo.yan@linaro.org>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Andy Gross <agross@kernel.org>,
        "Bjorn Andersson" <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>
CC: Mao Jinlong <quic_jinlmao@quicinc.com>,
        <coresight@lists.linaro.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
        <devicetree@vger.kernel.org>,
        Tingwei Zhang <quic_tingweiz@quicinc.com>,
        Yuanfang Zhang <quic_yuanfang@quicinc.com>,
        "Tao Zhang" <quic_taozha@quicinc.com>,
        Hao Zhang <quic_hazha@quicinc.com>
Subject: [PATCH v2 0/3] Add support for a streaming interface for TMC ETR
Date: Sun, 13 Aug 2023 23:12:50 +0800
Message-ID: <20230813151253.38128-1-quic_jinlmao@quicinc.com>
MIME-Version: 1.0
Content-Type: text/plain
Precedence: bulk

Series

Add support for a streaming interface for TMC ETR | expand

Message

Mao Jinlong Aug. 13, 2023, 3:12 p.m. UTC

This patch series is to add support for a streaming interface for
TMC ETR to allow for continuous log collection to secondary storage.
An interrupt based mechanism is used to stream out the data from the device.

QDSS_CS_QDSSCSR_ETRIRQCTRL register is used to set the IRQ byte counter
value. The value of this registers defines the number of bytes that when moved by
the ETR AXI interface. It will casues an interrupt which can be used by an
userspace program to know how much data is present in memory requiring copy to some
other location. A zero setting disables the interrupt.A one setting
means 8 bytes, two 16 bytes, etc. In other words, the value in this
register is the interrupt threshold times 8 bytes. ETR must be enabled
when use this interrupt function.

Sample:
echo 4096 > /sys/bus/coresight/devices/csr0/etr_byte_cntr_val
echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink
echo 1 > /sys/bus/coresight/devices/stm0/enabl_source

cat /dev/byte-cntr > /data/qdss.bin &

The log collection will stop after disabling the ETR.

codelinaro link:
https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/coresight-byte-cntr-v2?ref_type=heads

Change in V2:
Make CSR device as a helper device of ETR device. When enable ETR, it
will enable CSR byte-cntr function.

Mao Jinlong (3):
  Coresight: Add driver to support for CSR
  dt-bindings: arm: Adds CoreSight CSR hardware definitions
  coresight-csr: Add support for streaming interface for ETR

 .../testing/sysfs-bus-coresight-devices-csr   |   6 +
 .../bindings/arm/qcom,coresight-csr.yaml      | 130 ++++++
 MAINTAINERS                                   |   2 +-
 drivers/hwtracing/coresight/Kconfig           |  12 +
 drivers/hwtracing/coresight/Makefile          |   2 +
 drivers/hwtracing/coresight/coresight-core.c  |  31 +-
 .../coresight/coresight-csr-bytecntr.c        | 275 ++++++++++++
 .../hwtracing/coresight/coresight-csr-core.c  | 393 ++++++++++++++++++
 drivers/hwtracing/coresight/coresight-csr.h   | 112 +++++
 drivers/hwtracing/coresight/coresight-priv.h  |   8 +
 .../hwtracing/coresight/coresight-tmc-etr.c   |   3 +-
 drivers/hwtracing/coresight/coresight-tmc.h   |   2 +
 include/dt-bindings/arm/coresight-csr-dt.h    |  12 +
 include/linux/coresight.h                     |   3 +-
 14 files changed, 984 insertions(+), 7 deletions(-)
 create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-csr
 create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml
 create mode 100644 drivers/hwtracing/coresight/coresight-csr-bytecntr.c
 create mode 100644 drivers/hwtracing/coresight/coresight-csr-core.c
 create mode 100644 drivers/hwtracing/coresight/coresight-csr.h
 create mode 100644 include/dt-bindings/arm/coresight-csr-dt.h