| Message ID | 20230827115033.935089-1-dmitry.baryshkov@linaro.org |
|---|---|
| Headers | show |
| Series | ARM: qcom: apq8064: support CPU frequency scaling | expand |
On 27.08.2023 13:50, Dmitry Baryshkov wrote: > The SPM / SAW2 device also provides a voltage regulator functionality > with optional AVS (Adaptive Voltage Scaling) support. The exact register > sequence and voltage ranges differs from device to device. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On 27.08.2023 13:50, Dmitry Baryshkov wrote: > Add device node for the clock controller for the CPU cores and L2 > clocks. It will be further used by the L2 and by the CPUfreq nodes. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 26 ++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > index ba7d5ef8de17..a05e64bff07f 100644 > --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > @@ -213,6 +213,32 @@ sleep_clk: sleep_clk { > }; > }; > > + kraitcc: clock-controller { > + compatible = "qcom,krait-cc-v1"; > + clocks = <&gcc PLL9>, > + <&gcc PLL10>, > + <&gcc PLL16>, > + <&gcc PLL17>, > + <&gcc PLL12>, > + <&acc0>, > + <&acc1>, > + <&acc2>, > + <&acc3>, > + <&l2cc>; > + clock-names = "hfpll0", > + "hfpll1", > + "hfpll2", > + "hfpll3", > + "hfpll_l2", > + "acpu0_aux", > + "acpu1_aux", > + "acpu2_aux", > + "acpu3_aux", > + "acpu_l2_aux"; > + #clock-cells = <1>; > + #interconnect-cells = <1>; Doesn't only the L2 device register with icc? Konrad
On Mon, 28 Aug 2023 at 13:54, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > On 27.08.2023 13:50, Dmitry Baryshkov wrote: > > Add device node for the clock controller for the CPU cores and L2 > > clocks. It will be further used by the L2 and by the CPUfreq nodes. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > --- > > arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 26 ++++++++++++++++++++++++ > > 1 file changed, 26 insertions(+) > > > > diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > > index ba7d5ef8de17..a05e64bff07f 100644 > > --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > > +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > > @@ -213,6 +213,32 @@ sleep_clk: sleep_clk { > > }; > > }; > > > > + kraitcc: clock-controller { > > + compatible = "qcom,krait-cc-v1"; > > + clocks = <&gcc PLL9>, > > + <&gcc PLL10>, > > + <&gcc PLL16>, > > + <&gcc PLL17>, > > + <&gcc PLL12>, > > + <&acc0>, > > + <&acc1>, > > + <&acc2>, > > + <&acc3>, > > + <&l2cc>; > > + clock-names = "hfpll0", > > + "hfpll1", > > + "hfpll2", > > + "hfpll3", > > + "hfpll_l2", > > + "acpu0_aux", > > + "acpu1_aux", > > + "acpu2_aux", > > + "acpu3_aux", > > + "acpu_l2_aux"; > > + #clock-cells = <1>; > > + #interconnect-cells = <1>; > Doesn't only the L2 device register with icc? True. I'll drop this -- With best wishes Dmitry
On Sun, Aug 27, 2023 at 02:50:14PM +0300, Dmitry Baryshkov wrote: > The L2 cache device on Qualcomm Krait platforms controls the supplying > voltages and the cache frequency. Add corresponding bindings for this > device. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../bindings/cache/qcom,krait-l2-cache.yaml | 86 +++++++++++++++++++ > include/dt-bindings/soc/qcom,krait-l2-cache.h | 12 +++ > 2 files changed, 98 insertions(+) > create mode 100644 Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml > create mode 100644 include/dt-bindings/soc/qcom,krait-l2-cache.h > > diff --git a/Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml b/Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml > new file mode 100644 > index 000000000000..59ce11dd0a24 > --- /dev/null > +++ b/Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml > @@ -0,0 +1,86 @@ > +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) 'only', not 'or-later' With that, Reviewed-by: Rob Herring <robh@kernel.org> > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/cache/qcom,krait-l2-cache.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Krait L2 Cache > + > +maintainers: > + - Bjorn Andersson <andersson@kernel.org> > + > +description: > + L2 cache on Qualcomm Krait platforms is shared between all CPU cores. L2 > + cache frequency and voltages should be scaled according to the needs of the > + cores. > + > +allOf: > + - $ref: /schemas/cache-controller.yaml# > + > +select: > + properties: > + compatible: > + contains: > + enum: > + - qcom,krait-l2-cache > + > + required: > + - compatible > + > +properties: > + compatible: > + items: > + - const: qcom,krait-l2-cache > + - const: cache > + > + clocks: > + maxItems: 1 > + > + '#interconnect-cells': > + const: 1 > + > + vdd-mem-supply: > + description: suppling regulator for the memory cells of the cache > + > + vdd-dig-supply: > + description: suppling regulator for the digital logic of the cache > + > + operating-points-v2: true > + opp-table: > + type: object > + > +required: > + - compatible > + - cache-level > + - cache-unified > + - clocks > + - '#interconnect-cells' > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/soc/qcom,krait-l2-cache.h> > + > + l2-cache { > + compatible = "qcom,krait-l2-cache", "cache"; > + cache-level = <2>; > + cache-unified; > + vdd-mem-supply = <&pm8921_l24>; > + vdd-dig-supply = <&pm8921_s3>; > + clocks = <&kraitcc 4>; > + #interconnect-cells = <1>; > + operating-points-v2 = <&l2_opp_table>; > + > + l2_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-384000000 { > + opp-hz = /bits/ 64 <384000000>; > + opp-microvolt = <1050000 1050000 1150000>, > + <950000 950000 1150000>; > + }; > + }; > + }; > +... > + > diff --git a/include/dt-bindings/soc/qcom,krait-l2-cache.h b/include/dt-bindings/soc/qcom,krait-l2-cache.h > new file mode 100644 > index 000000000000..c9a38d368111 > --- /dev/null > +++ b/include/dt-bindings/soc/qcom,krait-l2-cache.h > @@ -0,0 +1,12 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (C) 2023 Linaro Ltd. All rights reserved. > + */ > + > +#ifndef __DT_BINDINGS_SOC_QCOM_KRAIT_L2_CACHE_H > +#define __DT_BINDINGS_SOC_QCOM_KRAIT_L2_CACHE_H > + > +#define MASTER_KRAIT_L2 0 > +#define SLAVE_KRAIT_L2 1 > + > +#endif > -- > 2.39.2 >
Implement CPUFreq support for one of the oldest supported Qualcomm platforms, APQ8064. Each core has independent power and frequency control. Additionally the L2 cache is scaled to follow the CPU frequencies (failure to do so results in strange semi-random crashes). Core voltage is controlled through the SAW2 devices, one for each core. The L2 has two regulators, vdd-mem and vdd-dig. Dependencies: [1], [2]. [1] https://lore.kernel.org/linux-arm-msm/20230827005920.898719-1-dmitry.baryshkov@linaro.org/ [2] https://lore.kernel.org/linux-arm-msm/20230827032803.934819-1-dmitry.baryshkov@linaro.org/ Changes since v3: - Split the opp and cpufreq patches to a separate series (Viresh) - Added the cache's select clause (Rob, Krzysztof) - Fixed $ref to include full path (Krzysztof) - Renamed opp-table-l2 to just opp-table (Krzysztof) - Unrolled loops in krait_l2_config_regulators() (Konrad) - Dropped useless comments from krait-cc DT (Konrad) - Fixed Votlage comment formatting (Konrad) - Added empty lines between nvmem cells (Konrad) - Replaced direct register masks with GENMASK (Konrad) - Reordered headers in spm.c (Konrad) Changes since v2: - Merged basic cpufreq and voltage patches, to make sure that we don't undervolt the cores (Konrad) - Reordered patches pushing voltage constraints early (Konrad) - Removed KRAIT_NUM_CLOCKS from the kraitcc bindings header (Konrad) - Rebased on top of PMIC cleanup - Added missing regulator constraints to apq8064-cm-qs600 and apq8064-sony-xperia-lagan-yuga. Changes since v1: - Added separate Krait L2 cache device driver - Moved vdd-mem and vdd-dig scaling to the L2 cache device (Christian, Stephen Gerhold) - Fixed the 'INTERCONNECT' in the guarding define for krait-cc bindings (Stephen Boyd) - Made SAW2's regulator property -> node handling clear (Krzysztof) - Dropped the 'regulator' property from all SAW2 devices. Dmitry Baryshkov (23): dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml dt-bindings: soc: qcom: qcom,saw2: define optional regulator node dt-bindings: clock: qcom,krait-cc: Krait core clock controller dt-bindings: cache: describe L2 cache on Qualcomm Krait platforms interconnect: icc-clk: add support for scaling using OPP clk: qcom: krait-cc: rewrite driver to use clk_hw instead of clk soc: qcom: spm: add support for voltage regulator soc: qcom: Add driver for Qualcomm Krait L2 cache scaling ARM: dts: qcom: apq8064-asus-nexus7-flo: constraint cpufreq regulators ARM: dts: qcom: apq8064-cm-qs600: constraint cpufreq regulators ARM: dts: qcom: apq8064-ifc6410: constraint cpufreq regulators ARM: dts: qcom: apq8064-sony-xperia-lagan-yuga: constraint cpufreq regulators ARM: dts: qcom: apq8064: rename SAW nodes to power-manager ARM: dts: qcom: apq8064: declare SAW2 regulators ARM: dts: qcom: apq8064: add Krait clock controller ARM: dts: qcom: apq8064: add L2 cache scaling ARM: dts: qcom: apq8064: add simple CPUFreq support ARM: dts: qcom: apq8064: enable passive CPU cooling ARM: dts: qcom: msm8960: declare SAW2 regulators ARM: dts: qcom: apq8084: drop 'regulator' property from SAW2 device ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device ARM: dts: qcom: ipq4019: drop 'regulator' property from SAW2 devices ARM: dts: qcom: ipq8064: drop 'regulator' property from SAW2 devices .../devicetree/bindings/arm/msm/qcom,saw2.txt | 58 -- .../bindings/cache/qcom,krait-l2-cache.yaml | 86 +++ .../qcom/{qcom,spm.yaml => qcom,saw2.yaml} | 39 +- .../dts/qcom/qcom-apq8064-asus-nexus7-flo.dts | 19 +- .../boot/dts/qcom/qcom-apq8064-cm-qs600.dts | 23 +- .../boot/dts/qcom/qcom-apq8064-ifc6410.dts | 23 +- .../qcom-apq8064-sony-xperia-lagan-yuga.dts | 13 +- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 670 +++++++++++++++++- arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 1 - arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 5 - arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 2 - arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 12 +- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 1 - drivers/clk/qcom/krait-cc.c | 141 ++-- drivers/interconnect/icc-clk.c | 13 +- drivers/soc/qcom/Kconfig | 9 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/krait-l2-cache.c | 160 +++++ drivers/soc/qcom/spm.c | 221 +++++- include/dt-bindings/clock/qcom,krait-cc.h | 15 + include/dt-bindings/soc/qcom,krait-l2-cache.h | 12 + include/linux/interconnect-clk.h | 1 + include/soc/qcom/spm.h | 9 + 23 files changed, 1357 insertions(+), 177 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt create mode 100644 Documentation/devicetree/bindings/cache/qcom,krait-l2-cache.yaml rename Documentation/devicetree/bindings/soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} (57%) create mode 100644 drivers/soc/qcom/krait-l2-cache.c create mode 100644 include/dt-bindings/clock/qcom,krait-cc.h create mode 100644 include/dt-bindings/soc/qcom,krait-l2-cache.h